📄 pld01a.vhd
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STS_OEn <= '0' when ( PLD_REG_OEn = '0' and ADDR( 8 downto 2 ) = "0000010" ) else '1';
STS_REG(0) <= CF_DETECT;
STS_REG(1) <= CF_BVD1;
STS_REG(2) <= CF_BVD2;
STS_REG(3) <= MMC_DETECT;
STS_REG(4) <= MMC_WP;
STS_REG(5) <= SIM_DETECTn;
STS_REG(6) <= MSINS;
STS_REG(7) <= POLL_FLAG;
STS_REG(8) <= USB1_WAKE;
STS_REG(9) <= SWAP_FLASH;
STS_REG(10) <= EXB_PRESn;
STS_REG(11) <= EX_IN0;
STS_REG(12) <= EX_IN1;
STS_REG(13) <= '0';
STS_REG(14) <= '0';
STS_REG(15) <= '0';
-- 0xA00000C Read
SW_OEn <= '0' when ( PLD_REG_OEn = '0' and ADDR( 8 downto 2 ) = "0000011" ) else '1';
SW_REG(0) <= SW1;
SW_REG(1) <= SW2;
SW_REG(2) <= SW3;
SW_REG(3) <= SW4_1;
SW_REG(4) <= SW4_2;
SW_REG(5) <= SW4_3;
SW_REG(6) <= DIP_DATA;
SW_REG(7) <= '0';
SW_REG(8) <= '0';
SW_REG(9) <= '0';
SW_REG(10) <= '0';
SW_REG(11) <= '0';
SW_REG(12) <= '0'; -- Board ID ( BDT017 = 0, BDT018 = 1 )
SW_REG(13) <= '0';
SW_REG(14) <= '0';
SW_REG(15) <= '0';
-- Interrupt Clear
INT_CLR <= '1' when ( PLD_REG_WRn = '0' and ADDR( 8 downto 2 ) = "0000100" ) else '0';
INT_OEn <= '0' when ( PLD_REG_OEn = '0' and ADDR( 8 downto 2 ) = "0000100" ) else '1';
ANY_CLR <= '1' when ( PLD_REG_WRn = '0' and ADDR( 8 downto 2 ) = "0000100" ) and
( (data(0) = '0') or
(data(1) = '0') or
(data(2) = '0') or
(data(3) = '0') or
(data(4) = '0') or
(data(5) = '0') or
(data(6) = '0') or
(data(7) = '0') or
(data(8) = '0') or
(data(9) = '0') or
(data(10) = '0') or
(data(11) = '0') or
(data(12) = '0') or
(data(13) = '0') or
(data(14) = '0') or
(data(15) = '0') )
else '0';
-- MMC/SD Control
process ( RESET_OUTn, MMC_DETECT, INT_CLR, DATA(0) )
begin
if ( RESET_OUTn = '0' ) then
MMC_IN_INT <= '0';
elsif ( INT_CLR = '1') then
MMC_IN_INT <= DATA(0);
elsif ( MMC_DETECT'event and MMC_DETECT = '1') then
MMC_IN_INT <= '1';
end if;
end process;
process ( RESET_OUTn, MMC_DETECT, INT_CLR, DATA(1) )
begin
if ( RESET_OUTn = '0' ) then
MMC_OUT_INT <= '0';
elsif ( INT_CLR = '1') then
MMC_OUT_INT <= DATA(1);
elsif ( MMC_DETECT'event and MMC_DETECT = '0') then
MMC_OUT_INT <= '1';
end if;
end process;
-- USIM Card Control
process ( RESET_OUTn, SIM_DETECTn, INT_CLR, DATA(2) )
begin
if ( RESET_OUTn = '0' ) then
SIM_IN_INT <= '0';
elsif ( INT_CLR = '1') then
SIM_IN_INT <= DATA(2);
elsif ( SIM_DETECTn'event and SIM_DETECTn = '0') then
SIM_IN_INT <= '1';
end if;
end process;
process ( RESET_OUTn, SIM_DETECTn, INT_CLR, DATA(3) )
begin
if ( RESET_OUTn = '0' ) then
SIM_OUT_INT <= '0';
elsif ( INT_CLR = '1') then
SIM_OUT_INT <= DATA(3);
elsif ( SIM_DETECTn'event and SIM_DETECTn = '1') then
SIM_OUT_INT <= '1';
end if;
end process;
-- USB Control
process ( RESET_OUTn, USB1_WAKE, INT_CLR, DATA(4) )
begin
if ( RESET_OUTn = '0' ) then
USB_IN_INT <= '0';
elsif ( INT_CLR = '1') then
USB_IN_INT <= DATA(4);
elsif ( USB1_WAKE'event and USB1_WAKE = '1') then
USB_IN_INT <= '1';
end if;
end process;
process ( RESET_OUTn, USB1_WAKE, INT_CLR, DATA(5) )
begin
if ( RESET_OUTn = '0' ) then
USB_OUT_INT <= '0';
elsif ( INT_CLR = '1') then
USB_OUT_INT <= DATA(5);
elsif ( USB1_WAKE'event and USB1_WAKE = '0') then
USB_OUT_INT <= '1';
end if;
end process;
-- CF Control
CF_DETECT <= not CF_CD1n and not CF_CD2n;
process ( RESET_OUTn, CF_DETECT, INT_CLR, DATA(6) )
begin
if ( RESET_OUTn = '0' ) then
CF_IN_INT <= '0';
elsif ( INT_CLR = '1') then
CF_IN_INT <= DATA(6);
elsif ( CF_DETECT'event and CF_DETECT = '1') then
CF_IN_INT <= '1';
end if;
end process;
process ( RESET_OUTn, CF_DETECT, INT_CLR, DATA(7) )
begin
if ( RESET_OUTn = '0' ) then
CF_OUT_INT <= '0';
elsif ( INT_CLR = '1') then
CF_OUT_INT <= DATA(7);
elsif ( CF_DETECT'event and CF_DETECT = '0') then
CF_OUT_INT <= '1';
end if;
end process;
-- Switch Control
process ( RESET_OUTn, SW1, INT_CLR, DATA(8) )
begin
if ( RESET_OUTn = '0' ) then
SW1_INT <= '0';
elsif ( INT_CLR = '1') then
SW1_INT <= DATA(8);
elsif ( SW1'event and SW1 = '0') then
SW1_INT <= '1';
end if;
end process;
process ( RESET_OUTn, SW2, INT_CLR, DATA(9) )
begin
if ( RESET_OUTn = '0' ) then
SW2_INT <= '0';
elsif ( INT_CLR = '1') then
SW2_INT <= DATA(9);
elsif ( SW2'event and SW2 = '0') then
SW2_INT <= '1';
end if;
end process;
process ( RESET_OUTn, SW3, INT_CLR, DATA(10) )
begin
if ( RESET_OUTn = '0' ) then
SW3_INT <= '0';
elsif ( INT_CLR = '1') then
SW3_INT <= DATA(10);
elsif ( SW3'event and SW3 = '0') then
SW3_INT <= '1';
end if;
end process;
process ( RESET_OUTn, SW4_1, INT_CLR, DATA(11) )
begin
if ( RESET_OUTn = '0' ) then
SW4_1INT <= '0';
elsif ( INT_CLR = '1') then
SW4_1INT <= DATA(11);
elsif ( SW4_1'event and SW4_1 = '0') then
SW4_1INT <= '1';
end if;
end process;
process ( RESET_OUTn, SW4_2, INT_CLR, DATA(12) )
begin
if ( RESET_OUTn = '0' ) then
SW4_2INT <= '0';
elsif ( INT_CLR = '1') then
SW4_2INT <= DATA(12);
elsif ( SW4_2'event and SW4_2 = '0') then
SW4_2INT <= '1';
end if;
end process;
process ( RESET_OUTn, SW4_3, INT_CLR, DATA(13) )
begin
if ( RESET_OUTn = '0' ) then
SW4_3INT <= '0';
elsif ( INT_CLR = '1') then
SW4_3INT <= DATA(13);
elsif ( SW4_3'event and SW4_3 = '0') then
SW4_3INT <= '1';
end if;
end process;
INT_REG(0) <= MMC_IN_INT;
INT_REG(1) <= MMC_OUT_INT;
INT_REG(2) <= SIM_IN_INT;
INT_REG(3) <= SIM_OUT_INT;
INT_REG(4) <= USB_IN_INT;
INT_REG(5) <= USB_OUT_INT;
INT_REG(6) <= CF_IN_INT;
INT_REG(7) <= CF_OUT_INT;
INT_REG(8) <= SW1_INT;
INT_REG(9) <= SW2_INT;
INT_REG(10) <= SW3_INT;
INT_REG(11) <= SW4_1INT;
INT_REG(12) <= SW4_2INT;
INT_REG(13) <= SW4_3INT;
INT_REG(14) <= '0';
INT_REG(15) <= '0';
INT_SET <= '1' when ( INT_REG(0) = '1' or
INT_REG(1) = '1' or
INT_REG(2) = '1' or
INT_REG(3) = '1' or
INT_REG(4) = '1' or
INT_REG(5) = '1' or
INT_REG(6) = '1' or
INT_REG(7) = '1' or
(INT_REG(8) = '1' and SW_INT_MASK = '0') or
(INT_REG(9) = '1' and SW_INT_MASK = '0') or
(INT_REG(10) = '1' and SW_INT_MASK = '0') or
(INT_REG(11) = '1' and SW_INT_MASK = '0') or
(INT_REG(12) = '1' and SW_INT_MASK = '0') or
(INT_REG(13) = '1' and SW_INT_MASK = '0') or
INT_REG(14) = '1' or
INT_REG(15) = '1' )
else '0';
CPLD_INTn <= '0' when ( INT_SET = '1' ) and ( ANY_CLR = '0' ) else '1';
DATA(15 downto 0) <= BCR1_REG(15 downto 0) when BCR1_OEn = '0' else
BCR2_REG(15 downto 0) when BCR2_OEn = '0' else
STS_REG(15 downto 0) when STS_OEn = '0' else
SW_REG(15 downto 0) when SW_OEn = '0' else
INT_REG(15 downto 0) when INT_OEn = '0' else
(others => 'Z');
-- MSINS Pull-Up Control
MS_PULL <= not MMC_DETECT or BCR1_REG(15);
------------------------- Reserve Pin -------------------------
TX_OUT0 <= TX_IN0;
TX_OUT1 <= TX_IN1;
end pld01a_ctl;
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