pld01a.vhd

Liod平台CPLD源代码 pxa270

--
--  51Board Electronic Technology Co., LTD.
--   
--   XSBase270-Core-G

--   Rev1.0 2006/06/05

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pld01a is

Port (

  -- INPUT

    ADDR25       : in std_logic; -- CPU ADDR
    ADDR         : in std_logic_vector(8 downto 2);
    DATA         : inout std_logic_vector(15 downto 0);

    CS0n         : in std_logic; -- CPU CSn
    CS1n         : in std_logic;
    CS2n         : in std_logic;
    CS3n         : in std_logic;
    CS4n         : in std_logic;
    CS5n         : in std_logic;
    RD_WRn       : in std_logic; -- CPU RD_WRn
    OEn          : in std_logic; -- CPU OEn
    WEn          : in std_logic; -- CPU WEn
    PCE1n        : in std_logic; -- CPU PCE1n
    PCE2n        : in std_logic; -- CPU PCE2n

    RESET_OUTn   : in std_logic; -- CPU RESET_OUTn
    MBGNT        : in std_logic; -- CPU MBGNT_SDCS3n
    DVAL1        : in std_logic; -- CPU DVAL1

    CF_BVD1      : in std_logic; -- CF Card BVD1
    CF_BVD2      : in std_logic; -- CF Card BVD2
    CF_CD1n      : in std_logic; -- CF Card Detect1
    CF_CD2n      : in std_logic; -- CF Card Detect2

    DIP_DATA     : in std_logic; -- DIP Switch Bit1
    USB1_WAKE    : in std_logic;

    EX_IN0       : in std_logic; -- Expansion Board INPUT
    EX_IN1       : in std_logic; -- Expansion Board INPUT

    MMC_DETECT   : in std_logic; -- MMC/SD Detect
    MMC_WP       : in std_logic; -- MMC/SD WP

    MSINS        : in std_logic;

    POLL_FLAG    : in std_logic; -- 2700G POLL_FLAG

    SIM_DETECTn  : in std_logic; -- SIM Card Detect

    SW1          : in std_logic; -- Push Switch1 input
    SW2          : in std_logic; -- Push Switch2 input
    SW3          : in std_logic; -- Push Switch3 input
    SW4_1        : in std_logic; -- 3 Position Switch input
    SW4_2        : in std_logic; -- 3 Position Switch input
    SW4_3        : in std_logic; -- 3 Position Switch input

    EXB_PRESn    : in std_logic; -- Expansion Board Present
    SWAP_FLASH   : in std_logic; -- Swap Flash bank chip selects

    TX_IN0       : in std_logic;
    TX_IN1       : in std_logic;

-- OUTPUT

    AUDIO_PWR_EN : out std_logic;
    BRDY_ENn     : out std_logic;
    CPLD_INTn    : out std_logic;
    CF_PWR_EN    : out std_logic; -- SIM Card Power Enable
    CF_RESET     : out std_logic;
    CF_OEn       : out std_logic;
    DAC_PWR_EN   : out std_logic;
    DATA_DIRn    : out std_logic; -- DATA Buffer Direction      Direction ("1"= A->B)
    DATA_OEn     : out std_logic; -- DATA Buffer Output Enable
    ADDR_DIRn    : out std_logic; -- ADDR Buffer Direction      Direction ("1"= A->B)
    ADDR_OEn     : out std_logic; -- ADDR Buffer Output Enable

    EX_FLASH_CSn : out std_logic; 
    EX_REG_CSn   : out std_logic; -- Expansion Board Register CSn

    FLASH_CSn    : out std_logic; -- Intel FlashROM CSn
    FLASH_RSTn   : out std_logic; -- Intel FlashROM RESETn

    HDD_PWR_EN   : out std_logic;

    IRDA_FSEL    : out std_logic;
    IRDA_MD0     : out std_logic;
    IRDA_MD1     : out std_logic;

    LAN_AEN      : out std_logic; -- LAN Controller CSn
    LAN_RESET    : out std_logic; -- LAN Controller RESET

    MMC_PWR_EN   : out std_logic; 
    MS_PWR_EN    : out std_logic; -- Memory Stick Power Enable
    MS_PULL      : out std_logic;

    PSKTSEL      : out std_logic;

    RS232_ON     : out std_logic;
    SLEEPn       : out std_logic;
    SPKR_OFF     : out std_logic;
    SYS_CS0n     : out std_logic;
    SYS_CS1n     : out std_logic;

    LCD_PWR_ON   : out std_logic;
    LED_REDn     : out std_logic;
    LED_GREENn   : out std_logic;

    USB_IDE_CSn  : out std_logic; 
    USB_IDE_RESn : out std_logic; 

    VBUS1_ON     : out std_logic;
    VGA_I2C_ENn  : out std_logic;

    EX_OUT0      : out std_logic; 
    EX_OUT1      : out std_logic;

    TX_OUT0      : out std_logic;
    TX_OUT1      : out std_logic

    );

end pld01a;

architecture pld01a_ctl of pld01a is

    signal PLD_REG_WRn  : std_logic;
    signal PLD_REG_OEn  : std_logic;
    signal CF_DETECT    : std_logic;
    signal BCR1_WRn     : std_logic;
    signal BCR1_OEn     : std_logic;
    signal BCR2_WRn     : std_logic;
    signal BCR2_OEn     : std_logic;
    signal STS_OEn      : std_logic;
    signal SW_OEn       : std_logic;
    signal MBREQ_EN     : std_logic;
    signal FLY_BY_EN    : std_logic;

    signal BCR1_REG     : std_logic_vector( 15 downto 0 );
    signal BCR2_REG     : std_logic_vector( 15 downto 0 );

    signal STS_REG      : std_logic_vector( 15 downto 0 );
    signal SW_REG       : std_logic_vector( 15 downto 0 );

    signal MMC_IN_INT   : std_logic;
    signal MMC_OUT_INT  : std_logic;
    signal CF_IN_INT    : std_logic;
    signal CF_OUT_INT   : std_logic;
    signal SIM_IN_INT   : std_logic;
    signal SIM_OUT_INT  : std_logic;
    signal USB_IN_INT   : std_logic;
    signal USB_OUT_INT  : std_logic;
    signal SW1_INT      : std_logic;
    signal SW2_INT      : std_logic;
    signal SW3_INT      : std_logic;
    signal SW4_1INT     : std_logic;
    signal SW4_2INT     : std_logic;
    signal SW4_3INT     : std_logic;

    signal INT_OEn      : std_logic;
    signal INT_CLR      : std_logic;
    signal ANY_CLR      : std_logic;
    signal INT_SET      : std_logic;
	signal SW_INT_MASK	: std_logic;
    signal INT_REG      : std_logic_vector( 15 downto 0 );

begin

 -- DATA Buffer Control

    DATA_DIRn   <= not(RD_WRn and (( not CS0n and SWAP_FLASH )			 ---	06.06.05 mbj rework
                            or ( not CS2n and PLD_REG_OEn )
                            or ( not CS3n )
                            or ( not CS4n )
                            or ( not PCE1n )
                            or ( not PCE2n )
                            or ( MBREQ_EN and OEn )
                            or ( FLY_BY_EN and not DVAL1 )
                            ));

    DATA_OEn    <= '0';

 -- ADDR Buffer Control
																							 ---	06.06.05 mbj rework
    ADDR_DIRn   <= not(MBREQ_EN and MBGNT);

    ADDR_OEn    <= '0';

 -- FlashROM Control

    FLASH_RSTn  <= RESET_OUTn;

    FLASH_CSn   <= not ( not CS0n and not SWAP_FLASH );

    EX_FLASH_CSn    <= not ( not CS0n and SWAP_FLASH );				

 -- 2700G Control

    SYS_CS0n    <= CS5n;
    SYS_CS1n    <= CS1n;

    BRDY_ENn    <= not CS5n;

 -- USB Control

    USB_IDE_CSn   <= CS4n;
    USB_IDE_RESn  <= RESET_OUTn;

 -- LAN Control

    LAN_AEN     <= CS3n;
    LAN_RESET   <= not RESET_OUTn;

 -- Expansion Board Register

    -- 0x8000000乣

    EX_REG_CSn  <= not ( not CS2n and not ADDR25 );
    EX_OUT0     <= not ( not CS2n and not ADDR25 );		---	06.06.05 mbj rework	,Expansion Board Register CSn

-- Board Control Register

    -- 0xA000000, 0xA000004 Read/Write

    PLD_REG_WRn <= not ( not CS2n and not RD_WRn and not WEn and ADDR25 );
    PLD_REG_OEn <= not ( not CS2n and     RD_WRn and not OEn and ADDR25 );

    BCR1_WRn    <= '0' when ( PLD_REG_WRn = '0' and ADDR( 8 downto 2 ) = "0000000" ) else '1';
    BCR1_OEn    <= '0' when ( PLD_REG_OEn = '0' and ADDR( 8 downto 2 ) = "0000000" ) else '1';

    process ( RESET_OUTn, BCR1_WRn )
    begin
      if ( RESET_OUTn = '0') then
        BCR1_REG(15 downto 0) <= "0111001000110000"; 
      elsif ( BCR1_WRn'event and BCR1_WRn = '1') then
        BCR1_REG(15 downto 0)  <= Data(15 downto 0);
      end if;
    end process;

    CF_PWR_EN    <= BCR1_REG(0) and CF_DETECT;
    CF_RESET     <= BCR1_REG(1);
    IRDA_FSEL    <= BCR1_REG(2);
    IRDA_MD0     <= BCR1_REG(3);
    IRDA_MD1     <= BCR1_REG(4);
    CF_OEn       <= BCR1_REG(5) or ( PCE1n and PCE2n );
    AUDIO_PWR_EN <= BCR1_REG(6);
    HDD_PWR_EN   <= BCR1_REG(7);

    LCD_PWR_ON   <= BCR1_REG(8);
    RS232_ON     <= BCR1_REG(9);
    PSKTSEL      <= BCR1_REG(10);
    SLEEPn       <= BCR1_REG(11);
    LED_REDn     <= BCR1_REG(12);
    LED_GREENn   <= BCR1_REG(13);
    SPKR_OFF     <= BCR1_REG(14);
    MMC_PWR_EN   <= BCR1_REG(15) and MMC_DETECT;

    BCR2_WRn    <= '0' when ( PLD_REG_WRn = '0' and ADDR( 8 downto 2 ) = "0000001" ) else '1';
    BCR2_OEn    <= '0' when ( PLD_REG_OEn = '0' and ADDR( 8 downto 2 ) = "0000001" ) else '1';

    process ( RESET_OUTn, BCR2_WRn )
    begin
      if ( RESET_OUTn = '0') then
        BCR2_REG(15 downto 0) <= "0000001000000000"; 
      elsif ( BCR2_WRn'event and BCR2_WRn = '1') then
        BCR2_REG(15 downto 0)  <= Data(15 downto 0);
      end if;
    end process;

    MS_PWR_EN    <= BCR2_REG(0) and not MSINS;
    VBUS1_ON     <= BCR2_REG(1);
    VGA_I2C_ENn  <= BCR2_REG(2);
    DAC_PWR_EN   <= BCR2_REG(3);
    MBREQ_EN     <= BCR2_REG(4);
    FLY_BY_EN    <= BCR2_REG(5);

   -- EX_OUT0      <= BCR2_REG(7);
    EX_OUT1      <= BCR2_REG(8);
	SW_INT_MASK  <= BCR2_REG(9);

    -- 0xA000008 Read