📄 yl2410_fs2440_dev.rpt
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cpldfit: version G.29 Xilinx Inc.
Fitter Report
Design Name: YL2410_FS2440_DEV Date: 7-23-2005, 9:46AM
Device Used: XC9536XL-5-VQ44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
20 /36 ( 56%) 20 /180 ( 11%) 5 /36 ( 14%) 34 /34 (100%) 21 /108 ( 19%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 13 13 | I/O : 28 0
Output : 20 20 | GCK/IO : 3 0
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 1 1 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 34 34
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 5
Non-registered Macrocell driving I/O 15
GLOBAL RESOURCES:
Signal 'CLKOUT0' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 20 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 20 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
BUF_nGCS0 1 1 FB2_14 STD FAST 22 I/O O
BUF_nOE 1 1 FB1_2 STD FAST 41 I/O O
BUF_nWE 1 1 FB1_4 STD FAST 42 I/O O
CF_nCS0 1 3 FB1_13 STD FAST 12 I/O O
CF_nCS1 1 3 FB1_14 STD FAST 13 I/O O
CPLD_USER<1> 1 1 FB1_16 STD FAST 16 I/O O RESET
CPLD_USER<2> 1 1 FB1_17 STD FAST 18 I/O O RESET
CPLD_USER<3> 1 1 FB2_17 STD FAST 19 I/O O RESET
CPLD_USER<4> 1 1 FB2_16 STD FAST 20 I/O O RESET
CPLD_USER<5> 1 1 FB2_15 STD FAST 21 I/O O RESET
CS8900_nCS 1 1 FB1_9 STD FAST 5 I/O O
DATABUF_DIR 1 1 FB2_7 STD FAST 32 I/O O
DATABUF_nOE 1 7 FB2_4 STD FAST 37 I/O O
DM9000_nCS 1 1 FB1_10 STD FAST 6 I/O O
IDE_DIOR 1 4 FB1_12 STD FAST 8 I/O O
IDE_DIOW 1 4 FB1_11 STD FAST 7 I/O O
LAN_nIOR 1 2 FB1_6 STD FAST 2 I/O O
LAN_nIOW 1 2 FB1_8 STD FAST 3 I/O O
RESET 1 1 FB2_2 STD FAST 38 I/O O
ST16C550_CS 1 1 FB1_15 STD FAST 14 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
ADDR23 FB2_3 36 GTS/I/O I
ADDR24 FB2_5 34 GTS/I/O I
CLKOUT0 FB1_3 43 GCK/I/O GCK/I
CLKOUT1 FB1_5 44 GCK/I/O I
nGCS0 FB1_7 1 GCK/I/O I
nGCS1 FB2_12 27 I/O I
nGCS2 FB2_11 28 I/O I
nGCS3 FB2_10 29 I/O I
nGCS4 FB2_13 23 I/O I
nGCS5 FB2_9 30 I/O I
nGCS7 FB2_8 31 I/O I
nOE FB2_1 39 I/O I
nRSTOUT_GPA21 FB2_6 33 GSR/I/O I
nWE FB1_1 40 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 13 10 10 13 13/0 17
FB2 7 11 11 7 7/0 17
---- ----- ----- -----
20 20 20/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 10/44
Number of signals used by logic mapping into function block: 10
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 40 I/O I
BUF_nOE 1 0 0 4 FB1_2 STD 41 I/O O
(unused) 0 0 0 5 FB1_3 43 GCK/I/O GCK/I
BUF_nWE 1 0 0 4 FB1_4 STD 42 I/O O
(unused) 0 0 0 5 FB1_5 44 GCK/I/O I
LAN_nIOR 1 0 0 4 FB1_6 STD 2 I/O O
(unused) 0 0 0 5 FB1_7 1 GCK/I/O I
LAN_nIOW 1 0 0 4 FB1_8 STD 3 I/O O
CS8900_nCS 1 0 0 4 FB1_9 STD 5 I/O O
DM9000_nCS 1 0 0 4 FB1_10 STD 6 I/O O
IDE_DIOW 1 0 0 4 FB1_11 STD 7 I/O O
IDE_DIOR 1 0 0 4 FB1_12 STD 8 I/O O
CF_nCS0 1 0 0 4 FB1_13 STD 12 I/O O
CF_nCS1 1 0 0 4 FB1_14 STD 13 I/O O
ST16C550_CS 1 0 0 4 FB1_15 STD 14 I/O O
CPLD_USER<1> 1 0 0 4 FB1_16 STD 16 I/O O
CPLD_USER<2> 1 0 0 4 FB1_17 STD 18 I/O O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: ADDR23 5: nGCS3 8: nGCS1
2: ADDR24 6: nOE 9: nGCS2
3: nWE 7: nGCS4 10: nGCS5
4: CLKOUT1
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
BUF_nOE .....X.................................. 1 1
BUF_nWE ..X..................................... 1 1
LAN_nIOR .X...X.................................. 2 2
LAN_nIOW .XX..................................... 2 2
CS8900_nCS ....X................................... 1 1
DM9000_nCS ......X................................. 1 1
IDE_DIOW XXX.....X............................... 4 4
IDE_DIOR XX...X..X............................... 4 4
CF_nCS0 XX.......X.............................. 3 3
CF_nCS1 XX.......X.............................. 3 3
ST16C550_CS .......X................................ 1 1
CPLD_USER<1> ...X.................................... 1 1
CPLD_USER<2> ...X.................................... 1 1
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 11/43
Number of signals used by logic mapping into function block: 11
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 39 I/O I
RESET 1 0 0 4 FB2_2 STD 38 I/O O
(unused) 0 0 0 5 FB2_3 36 GTS/I/O I
DATABUF_nOE 1 0 0 4 FB2_4 STD 37 I/O O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O I
(unused) 0 0 0 5 FB2_6 33 GSR/I/O I
DATABUF_DIR 1 0 0 4 FB2_7 STD 32 I/O O
(unused) 0 0 0 5 FB2_8 31 I/O I
(unused) 0 0 0 5 FB2_9 30 I/O I
(unused) 0 0 0 5 FB2_10 29 I/O I
(unused) 0 0 0 5 FB2_11 28 I/O I
(unused) 0 0 0 5 FB2_12 27 I/O I
(unused) 0 0 0 5 FB2_13 23 I/O I
BUF_nGCS0 1 0 0 4 FB2_14 STD 22 I/O O
CPLD_USER<5> 1 0 0 4 FB2_15 STD 21 I/O O
CPLD_USER<4> 1 0 0 4 FB2_16 STD 20 I/O O
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