yl2410_fs2440_dev.npl

来自「在文件夹YL2440_CPLD中有做好的CPLD工程」· NPL 代码 · 共 25 行

JDF G
// Created by Project Navigator ver 1.0
PROJECT YL2410_FS2440_DEV
DESIGN yl2410_fs2440_dev
DEVFAM xc9500xl
DEVFAMTIME 0
DEVICE xc9536xl
DEVICETIME 0
DEVPKG VQ44
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
SOURCE YL2410_FS2440_DEV.v
DEPASSOC YL2410_FS2440_DEV YL2410_FS2440_DEV_ucf.ucf
[STRATEGY-LIST]
Normal=True