frediv16.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册所配套源代码」· VHDL 代码 · 共 24 行

package test_con is
	constant N1:integer:=16;
end test_con;
use work.test_con.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity frediv16 is
port(clkin :in std_logic;
		clkout:out std_logic);
end frediv16;
architecture behav of frediv16 is 
component fredivn
	generic(N:positive);
	port (clk:in std_logic;
		outclk:out std_logic);
END component;
begin
u1:fredivn
	generic map(N=>N1)
	port map(clkin,clkout);
end behav;