sn74ls148.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity sn74ls148 is
port(i:in std_logic_vector(7 downto 0);
	s:in std_logic;
	ys,yex:out std_logic;
	y:out std_logic_vector(2 downto 0));
end sn74ls148;
architecture behav of sn74ls148 is
begin
ys<=NOT((NOT(s)) and ( i(0)) and ( i(1))and ( i(2))and ( i(3))and ( i(4))and ( i(5))and ( i(6))and ( i(7)));
yex<=NOT((NOT(s)) and ((NOT i(0))  or (NOT i(1)) or (NOT i(2)) or (NOT i(3)) or (NOT i(4)) or (NOT i(5)) or (NOT i(6)) or (NOT i(7))));
process(i,s)
begin
if(s='0')then
if(i(0)='0')then
y<="000";
elsif (i(1)='0')then
y<="001";
elsif (i(2)='0')then
y<="010";
elsif (i(3)='0')then
y<="011";
elsif (i(4)='0')then
y<="100";
elsif (i(5)='0')then
y<="101";
elsif (i(6)='0')then
y<="110";
elsif (i(7)='0')then
y<="111";
else 
y<="XXX";
end if;
end if;
end process;
end behav;