pulse_sequence.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity pulse_sequence is 
port (
		res:in std_logic;		--定义复位信号
		in1:in std_logic;		--定义8路输入脉冲信号
		in2:in std_logic;
		in3:in std_logic;
		in4:in std_logic;
		in5:in std_logic;
		in6:in std_logic;
		in7:in std_logic;
		in8:in std_logic;
		sequence_in1:out std_logic_vector(3 downto 0);		--定义8路输出相应脉冲次序号
		sequence_in2:out std_logic_vector(3 downto 0);
		sequence_in3:out std_logic_vector(3 downto 0);
		sequence_in4:out std_logic_vector(3 downto 0);
		sequence_in5:out std_logic_vector(3 downto 0);
		sequence_in6:out std_logic_vector(3 downto 0);
		sequence_in7:out std_logic_vector(3 downto 0);
		sequence_in8:out std_logic_vector(3 downto 0)
);
end pulse_sequence;
architecture beh of pulse_sequence is
signal 	temp:			std_logic_vector(3 downto 0); 	 --定义下一个即将到达的脉冲次序号
signal	sequence_flag1	: std_logic_vector(3 downto 0);--定义每路是否已有脉冲输入的标志
signal	sequence_flag2	: std_logic_vector(3 downto 0);
signal	sequence_flag3	: std_logic_vector(3 downto 0);
signal	sequence_flag4	: std_logic_vector(3 downto 0);
signal	sequence_flag5	: std_logic_vector(3 downto 0);
signal	sequence_flag6	: std_logic_vector(3 downto 0);
signal	sequence_flag7	: std_logic_vector(3 downto 0);
signal	sequence_flag8	: std_logic_vector(3 downto 0);
begin
temp<=sequence_flag1+sequence_flag2+sequence_flag3+sequence_flag4+sequence_flag5+sequence_flag6+sequence_flag7+sequence_flag8+"0001";--计算下一个即将到达的脉冲次序号
process(res,in1)								--监测第一路脉冲输入
begin
	if res = '1' then
sequence_in1 <= "0000";	--如果res为高电平则将sequence_in1和                 
		   sequence_flag1 <= "0000";          --sequence_flag1清零,开始重新判断
	else										
		if in1'event and in1='1' then			--若本路有脉冲到达
			if sequence_flag1 = "0000" then	--并且为第一次到达
				sequence_in1 <= temp;		--则将次序号赋给sequence_in1
				sequence_flag1 <= "0001";	--并将标志置1
			end if;
		end if;
	end if;
end process;
process(res,in2)
begin
	if res = '1' then
		sequence_in2 <= "0000";
		sequence_flag2 <= "0000";
	else
		if in2'event and in2='1' then
			if sequence_flag2 = "0000" then
				sequence_in2 <= temp;
				sequence_flag2 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in3)
begin
	if res = '1' then
		sequence_in3 <= "0000";
		sequence_flag3 <= "0000";
	else
		if in3'event and in3='1' then
			if sequence_flag3 = "0000" then
				sequence_in3 <= temp;
				sequence_flag3 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in4)
begin
	if res = '1' then
		sequence_in4 <= "0000";
		sequence_flag4 <= "0000";
	else
		if in4'event and in4='1' then
			if sequence_flag4 = "0000" then
				sequence_in4 <= temp;
				sequence_flag4 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in5)
begin
	if res = '1' then
		sequence_in5 <= "0000";
		sequence_flag5 <= "0000";
	else
		if in5'event and in5='1' then
			if sequence_flag5 = "0000" then
				sequence_in5 <= temp;
				sequence_flag5 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in6)
begin
	if res = '1' then
		sequence_in6 <= "0000";
		sequence_flag6 <= "0000";
	else
		if in6'event and in6='1' then
			if sequence_flag6 = "0000" then
				sequence_in6 <= temp;
				sequence_flag6 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in7)
begin
	if res = '1' then
		sequence_in7 <= "0000";
		sequence_flag7 <= "0000";
	else
		if in7'event and in7='1' then
			if sequence_flag7 = "0000" then
				sequence_in7 <= temp;
				sequence_flag7 <= "0001";			
			end if;
		end if;
	end if;
end process;
process(res,in8)
begin
	if res = '1' then
		sequence_in8 <= "0000";
		sequence_flag8 <= "0000";
	else
		if in8'event and in8='1' then
			if sequence_flag8 = "0000" then
				sequence_in8 <= temp;
				sequence_flag8 <= "0001";			
			end if;
		end if;
	end if;
end process;
end beh;