show.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册所配套源代码」· VHDL 代码 · 共 22 行

--show 模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity show is 
port(
      indata:in std_logic_vector(11 downto 0);
      led1,led2,led3:out std_logic_vector(3 downto 0)
     );
end show;

architecture behave of show is 
begin
     process
     begin
     led1<=indata(3 downto 0);
     led2<=indata(7 downto 4);
     led3<=indata(11 downto 8);
     end process;
end behave;