sel_ampl.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

--SEL_ampl 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sel_ampl is
port (
       key: in std_logic_vector(1 downto 0);
       ampl:in std_logic_vector(9 downto 0);
       in1: in std_Logic_vector(7 downto 0);--sine function;
       in2: in std_logic;--Squad wave
       in3: in std_logic_vector(5 downto 0);--Triangle Function
       dout: out std_logic_vector(9 downto 0);--Data output;
       led1: out std_logic_vector(6 downto 0)--led1 indicates the types of wave;
      );
end sel_ampl;

architecture beh of sel_ampl is
begin
 process(key)
       variable temp: std_logic_vector(9 downto 0);
       variable temp2:std_logic_vector(9 downto 0);
       variable temp1:std_logic_vector(9 downto 0);
    begin
       temp(1 downto 0):=ampl(4 downto 3);
       temp(9 downto 2):="00000000";
       temp2(3 downto 0):=ampl(6 downto 3);
       temp2(9 downto 4):="000000";
       case key is
       when "01" =>--正弦波
                   temp1:=temp1(1 downto 0)*in1+in1;
                   dout<=temp1;
                   led1<="1111001";--显示数字'1';
	   when "10" =>--方波
				case in2 is
					when '1'=> dout<=ampl;
					when others=>dout<="0000000000";
				end case;
				led1 <="0100100";--显示数字'2';
	  when "11" =>--三角波
      			temp1:=temp2(3 downto 0)*in3+in3;
                dout<=temp1;
       			led1<="0110000";--显示数字'3';
	 when others =>
     			dout<="0000000000";
      	        led1<="1111111";--不显示
  	 end case;
end process;
end beh;