dis_sig.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

--dis_sig 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity dis_sig is
port(
key:in std_logic;
selsig:out std_logic;
selout:out std_logic_vector(2 downto 0);
sel_show: out std_logic
    );
end dis_sig;

architecture behave of dis_sig is
begin
process(key)
variable temp:std_logic;
begin
wait until key'event and key='0';
 temp:=not temp;
 selsig<=temp;
 if temp='0' then
    selout<="100";
    sel_show<='0';
elsif temp='1' then
    selout <="111";
    sel_show<='1';
end if;
      end process;
end behave;