updown.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

--updown (of testup)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity updown is 
port(r_in:in std_logic;
	 key:in std_logic;
	 s_in:in std_logic;
	 sys_clk:in std_logic;
	 dataout:out std_logic_vector(9 downto 0));
end updown;

architecture behave of updown is
signal clk: std_logic;
signal data: std_logic_vector(9 downto 0);
begin
   process(sys_clk)
   begin
   if sys_clk'event and sys_clk='0' then
     clk<=(r_in and s_in);
   end if;
   end process;
   process(clk)
   begin
         if clk'event and clk='0' then
               if key='1' then
                  data<=data+8;
               else
                   data<=data-8;
               end if;
         end if;
     end process;
        dataout<=data;
end behave;