add_a_f.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

--addr_a_f
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity addr_a_f is
port(
      sel: in std_logic_vector( 1 downto 0);
      sel_a_f: in std_logic;
      ampl: in std_logic_vector(9 downto 0);
      freq: in std_logic_vector(6 downto 0);
      addr: out std_logic_vector(7 downto 0)
    );
end addr_a_f;
architecture beh of addr_a_f is
begin
    process(sel,ampl)
    variable sin: std_logic_vector(1 downto 0);
    variable sanjiao: std_logic_vector(3 downto 0);
    variable fangbo: std_logic_vector(6 downto 0);
    begin
      if sel_a_f='0' then
       sin:=ampl(4 downto 3);
       fangbo:=ampl(9 downto 3);
        sanjiao:=ampl(6 downto 3);
        case sel is
         when "01" =>addr<='l' & sin & "11111";
         when "10" =>addr<='l' & fangbo;
         when "11" =>addr<='l' & sanjiao & "111";
         when others =>null;
         end case;

      elsif sel_a_f='1' then
          addr<='0' & freq;
       end if;
     end process;
end beh;