mul3.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;

entity mul3 is
port(in1,in2,in3:std_logic_vector(7 downto 0);
     sela,selb,selc:in std_logic;
     dout:out std_logic_vector(7 downto 0)
     );
end mul3;
architecture behav of mul3 is
signal sel:std_logic_vector(2 downto 0);
begin
process(sela,selb,selc)
begin
if sela='0' then dout<=in1;
elsif selb='0' then dout<=in2;
elsif selc='0' then dout<=in3;
end if;
end process;
end behav;