mul2wr.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;

entity mul2wr is
port(sel:in std_logic;
     in0,in1:std_logic;
     dout:out std_logic
     );
end mul2wr;
architecture behav of mul2wr is
begin
process(in1,in0,sel)
begin
if sel='1' then dout<=in1;
elsif sel='0' then dout<=in0;
end if;
end process;
end behav;