tone.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee;
use ieee.std_logic_1164.all;

entity tone is
port(
       index  :  in integer range 0 to 15;
       code   :  out std_logic_vector(6 downto 0);
       high   :  out std_logic_vector(6 downto 0);
       tone   :  out integer range 0 to 16#7ff#
     );
end tone;

architecture behave of tone is
begin
     process(index)
     begin
     case index is
         when 0 => tone<=2047; code<="1000000";   high<="1000000";
         when 1 => tone<=662; code<="1111001";   high<="1000000";
         when 2 => tone<=810; code<="0100100";   high<="1000000";
         when 3 => tone<=942; code<="0110000";   high<="1000000";
         when 4 => tone<=1032; code<="0011001";   high<="1000000";
         when 5 => tone<=1100; code<="0010010";   high<="1000000";
         when 6 => tone<=1200; code<="0000010";   high<="1000000";
         when 7 => tone<=1329; code<="1111000";   high<="1000000";
         when 8 => tone<=17; code<="0000000";   high<="1111001";
         when 9 => tone<=239; code<="0010000";   high<="1111001";
         when 10 => tone<=436; code<="0001000";   high<="1111001";
         when 11 => tone<=612; code<="0000011";   high<="1111001";
         when 12 => tone<=1370; code<="1000110";   high<="0100100";
         when 13 => tone<=1443; code<="0100001";   high<="0100100";
         when 14 => tone<=1509; code<="0000110";   high<="0100100";
         when 15 => tone<=1540; code<="0001110";   high<="0100100";
         when others=>null;
     end case;
    end process;
end behave;