rxt.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity rxt is
port(
	mclk_16:in std_logic;--16倍baud
	rx:in std_logic;--读，复位，和接收端
	data:out std_logic_vector(7 downto 0)
	);
end rxt;
architecture behave of rxt is 
signal mclk:std_logic;--baud;
--signal recreg:std_logic_vector(7 downto 0);--采样计数位
signal cnt:std_logic_vector(3 downto 0);
begin


rx_clk:process(mclk_16) 
begin
	if(mclk_16'event and mclk_16='1')then
		if(cnt="0111") then
			cnt<="0000";
		else
			cnt<=cnt+'1';
		end if;
 	 end if;
	end process;
end behave;