butterfly1.vhd

CPLDFPGA嵌入式应用开发技术白金手册所配套源代码

library lpm;
use lpm.lpm_components.all;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity butterfly1 is
        generic(w2:integer:=17;       --乘法数位宽
            w1:integer:=9;        --c+s和的位宽
            w:integer:=8);        --输入位宽
        port(clk:std_logic;
             are_in,aim_in,c_in,bre_in,bim_in:in std_logic_vector(w-1 downto 0);                        --8位输入
             cps_in,cms_in:in std_logic_vector(w1-1 downto 0);--9位系数
             dre_out,dim_out,ere_out,eim_out:out std_logic_vector(w-1 downto 0));                       --8位结果
end butterfly1;

architecture bf of butterfly1 is 
   signal dif_re,dif_im:std_logic_vector(w-1 downto 0);
   signal are,aim,bre,bim:integer range -128 to 127;
   signal c:std_logic_vector(w-1 downto 0);
   signal cps,cms:std_logic_vector(w1-1 downto 0);  --输入系数
   signal cre,cim:std_logic_vector(w1-1 downto 0);
component ccmul
generic(w2:positive;       --乘法数位宽
            w1:positive;        --c+s和的位宽
            w:positive);        --输入位宽
    port(clk:std_logic;           --输出寄存器的时钟
         x_in,y_in,c_in:in std_logic_vector(w-1 downto 0);
         cps_in,cms_in:in std_logic_vector(w1-1 downto 0);
         r_out,i_out:out std_logic_vector(w-1 downto 0));
end component;

begin
   process                  --整数和输入寄存在FF中
      begin
         wait until clk='1';
         are<=conv_integer(are_in);
	 aim<=conv_integer(aim_in);
	 bre<=conv_integer(bre_in);
	 bim<=conv_integer(bim_in);
 	 c<=c_in;		 --从内存中加载cos
	 cps<=cps_in;		 --从内存中加载cos+sin
	 cms<=cms_in;		 --从内存中加载cos-sin
         dre_out<=conv_std_logic_vector((are+bre)/2,w);
	 dim_out<=conv_std_logic_vector((aim+bim)/2,w);
   end process;

process(are,bre,aim,bim)
begin
   dif_re<=conv_std_logic_vector((are-bre)/2,8);
   dif_im<=conv_std_logic_vector((aim-bim)/2,w);
end process;
--实例化复数旋转因子
ccmul_1:ccmul
     generic map(w2=>w,w1=>w1,w=>w)
     port map(clk=>clk,x_in=>dif_re,y_in=>dif_im,c_in=>c,cps_in=>cps,cms_in=>cms,r_out=>ere_out,i_out=>eim_out);

end bf;