adder4bit.vhd

来自「CPLDFPGA嵌入式应用开发技术白金手册所配套源代码」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity adder4bit is
   port(cin:in std_logic;
	a,b:in std_logic_vector(3 downto 0);
	s:out std_logic_vector(3 downto 0);
	cout:out std_logic);
end adder4bit;

architecture beh of adder4bit is
    signal sint:std_logic_vector(4 downto 0);
    signal aa,bb:std_logic_vector(4 downto 0);
 begin
    aa<='0' & a(3 downto 0);      --4位加数矢量扩为5位，提供进位空间
    bb<='0' & b(3 downto 0); 
    sint<=aa+bb+cin;
    s(3 downto 0)<=sint(3 downto 0);
    cout<=sint(4);
end beh;