vrs51l3074_sdcc.h

RAMTRON 3047 C51所用的头文件 单周期8051 40MIPS

sfr at 0xF0              B;     // B                                                                         
sfr at 0xF1          MPAGE;     // External memory page select                                               
sfr at 0xF2     DEVCLKCFG1;     // Clock configuration 1                                                     
sfr at 0xF3     DEVCLKCFG2;     // Clock configuration 2                                                     
sfr at 0xF4      PERIPHEN1;     // Perhipheral enable 1                                                      
sfr at 0xF5      PERIPHEN2;     // Perhipheral enable 2                                                      
sfr at 0xF6      DEVMEMCFG;     // Memory control                                                            
sfr at 0xF7       PORTINEN;     // Port input logic enable                                                   
sfr at 0xF8      USERFLAGS;     // Additional software flags                                                 
sfr at 0xF9       P0PINCFG;     // Port 0 pin configuration                                                  
sfr at 0xFA       P1PINCFG;     // Port 1 pin configuration                                                  
sfr at 0xFB       P2PINCFG;     // Port 2 pin configuration                                                  
sfr at 0xFC       P3PINCFG;     // Port 3 pin configuration                                                  
sfr at 0xFD       P4PINCFG;     // Port 4 pin configuration                                                  
sfr at 0xFE       P5PINCFG;     // Port 5 pin configuration                                                  
sfr at 0xFF       P6PINCFG;     // Port 6 pin configuration                                                  

// SFRs that can be only be accessed on PAGE 0
// When DEVMEMCFG bit 0 = 0

sfr at 0x9E        PWC0CFG;     // Pulse Width Counter 0 configuration                                       
sfr at 0x9F        PWC1CFG;     // Pulse Width Counter 1 configuration                                       

sfr at 0xA1       UART0INT;     // UART 0 Interrupt                                                          
sfr at 0xA2       UART0CFG;     // UART 0 Configure                                                          
sfr at 0xA3       UART0BUF;     // UART 0 buffer                                                             
sfr at 0xA4       UART0BRL;     // UART 0 baud rate lower byte                                               
sfr at 0xA5       UART0BRH;     // UART 0 baud rate upper byte                                               
sfr at 0xA6       UART0EXT;     // UART 0 extentions                                                         

sfr at 0xA9         PWMCFG;     // Pulse Width Modulator configurations                                      
sfr at 0xAA          PWMEN;     // Pulse Width Modulator enable                                              
sfr at 0xAB       PWMLDPOL;     // / Pulse Width Modulator polarity                                          
sfr at 0xAC        PWMDATA;     // Pulse Width Modulator data                                                
sfr at 0xAD       PWMTMREN;     // Pulse Width Modulator timer enable                                        
sfr at 0xAE        PWMTMRF;     // Pulse Width Modulator timer overflow flags                                
sfr at 0xAF      PWMCLKCFG;     // Pulse Width Modulator clock config                                        
sfr at 0xB0       UART1INT;     // UART 1 Interrupt                                                          
sfr at 0xB1       UART1CFG;     // UART 1 Configure                                                          
sfr at 0xB2       UART1BUF;     // UART 1 buffer                                                             
sfr at 0xB3       UART1BRL;     // UART 1 baud rate lower byte                                               
sfr at 0xB4       UART1BRH;     // UART 1 baud rate upper byte                                               
sfr at 0xB5       UART1EXT;     // UART 1 extentions                                                         

sfr at 0xC1        SPICTRL;     // SPI (Serial Perhipheral Interface) control                                
sfr at 0xC2      SPICONFIG;     // SPI configurations                                                        
sfr at 0xC3        SPISIZE;     // SPI transaction size                                                      
sfr at 0xC4       SPIRXTX0;     // SPI recieve / transmit register 0 [Data  7: 0]                            
sfr at 0xC5       SPIRXTX1;     // SPI recieve / transmit register 0 [Data 15: 8]                            
sfr at 0xC6       SPIRXTX2;     // SPI recieve / transmit register 0 [Data 23:16]                            
sfr at 0xC7       SPIRXTX3;     // SPI recieve / transmit register 0 [Data 32:24]                            

sfr at 0xC9      SPISTATUS;     // SPI status                                                                

sfr at 0xD1      I2CCONFIG;     // I2C (Inter Chip Communication) configuration                              
sfr at 0xD2      I2CTIMING;     // I2C timing                                                                
sfr at 0xD3       I2CIDCFG;     // I2C indentification                                                       
sfr at 0xD4      I2CSTATUS;     // I2C status                                                                
sfr at 0xD5        I2CRXTX;     // I2C recieve / transmit buffer                                             

sfr at 0xDC       FRAMCFG1;     // FRAM configuration 1
sfr at 0xDD       FRAMCFG2;     // FRAM configuration 2

// SFRs that can be only be accessed on PAGE 1
// When DEVMEMCFG bit 0 = 1

sfr at 0xA2           AUA0;     // Arithmetic Unit A [ 7: 0]                                                 
sfr at 0xA3           AUA1;     // Arithmetic Unit A [15: 8]                                                 
sfr at 0xA4           AUC0;     // Arithmetic Unit C [ 7: 0]                                                 
sfr at 0xA5           AUC1;     // Arithmetic Unit C [15: 8]                                                 
sfr at 0xA6           AUC2;     // Arithmetic Unit C [23:16]                                                 
sfr at 0xA7           AUC3;     // Arithmetic Unit C [32:24]                                                 

sfr at 0xB1        AUB0DIV;     // Arithmetic Unit B Divide [ 7: 0]                                          
sfr at 0xB2           AUB0;     // Arithmetic Unit B Multiply [ 7: 0]                                        
sfr at 0xB3           AUB1;     // Arithmetic Unit B [15: 8]                                                 
sfr at 0xB4         AURES0;     // Arithmetic Unit Result 0                                                  
sfr at 0xB5         AURES1;     // Arithmetic Unit Result 1                                                  
sfr at 0xB6         AURES2;     // Arithmetic Unit Result 2                                                  
sfr at 0xB7         AURES3;     // Arithmetic Unit Result 3                                                  

sfr at 0xC1     AUSHIFTCFG;     // Arithmetic Unit shift configuration                                       
sfr at 0xC2      AUCONFIG1;     // Arithmetic Unit configuration 1                                           
sfr at 0xC3      AUCONFIG2;     // Arithmetic Unit configuration 2                                           
sfr at 0xC4        AUPREV0;     // Arithmetic Unit previous result 0                                         
sfr at 0xC5        AUPREV1;     // Arithmetic Unit previous result 1                                         
sfr at 0xC6        AUPREV2;     // Arithmetic Unit previous result 2                                         
sfr at 0xC7        AUPREV3;     // Arithmetic Unit previous result 3                                         

#endif
/**************************************************************************
* Copyright (C) 2006 Ramtron International Corporation
**************************************************************************/