vrs51l3074_sdcc.h

RAMTRON 3047 C51所用的头文件 单周期8051 40MIPS

/**************************************************************************
* File:    VRS51L3074_SDCC.h
* Version: 1.92
* Target:  SDCC - Small Device C Compiler
* Date:    4/27/2006 
***************************************************************************
*
* This file provides all of the SFR definitions described in the device
* datsheet.
*             
* DO NOT ACCESS REGISTER VALUES NOT ON THIS LIST
* Make sure that the page selected contains the SFR being accessed
*                 
* Copyright (C) 2006 Ramtron International Corporation
*
* SDCC is subject to the GNU General Public License
* http://www.gnu.org/copyleft/gpl.html
**************************************************************************/

#ifndef __VRS51L3074_SDCC_H__
#define __VRS51L3074_SDCC_H__

// Location of MPAGE for the SDCC compiler internals
// (For correct compiling of pdata variables)
sfr at 0xF1         _XPAGE;


// SFRs that can be accessed on either page

sfr at 0x80             P0;     // Port 0                                                                    
sfr at 0x81             SP;     // Stack pointer                                                             
sfr at 0x82           DPL0;     // Data Pointer 0 lower byte                                                 
sfr at 0x83           DPH0;     // Data Pointer 0 upper byte                                                 
sfr at 0x84           DPL1;     // Data Pointer 1 lower byte                                                 
sfr at 0x85           DPH1;     // Data Pointer 1 upper byte                                                 
sfr at 0x86            DPS;     // Data Pointer select                                                       
sfr at 0x87           PCON;     // Power control                                                             
sfr at 0x88         INTEN1;     // Interrupt enable 1                                                        
sfr at 0x89        T0T1CFG;     // Timer 0 and Timer 1 configuration                                         
sfr at 0x8A            TL0;     // Timer 0 lower byte                                                        
sfr at 0x8B            TH0;     // Timer 0 upper byte                                                        
sfr at 0x8C            TL1;     // Timer 1 lower byte                                                        
sfr at 0x8D            TH1;     // Timer 1 upper byte                                                        
sfr at 0x8E            TL2;     // Timer 2 lower byte                                                        
sfr at 0x8F            TH2;     // Timer 2 upper byte                                                        
sfr at 0x90             P1;     // Port 1                                                                    
sfr at 0x91         WDTCFG;     // Watchdog timer configuration                                              
sfr at 0x92         RCAP0L;     // Reload / Capture for Timer 0: lower byte                                  
sfr at 0x93         RCAP0H;     // Reload / Capture for Timer 0: upper byte                                  
sfr at 0x94         RCAP1L;     // Reload / Capture for Timer 1: lower byte                                  
sfr at 0x95         RCAP1H;     // Reload / Capture for Timer 1: upper byte                                  
sfr at 0x96         RCAP2L;     // Reload / Capture for Timer 2: lower byte                                  
sfr at 0x97         RCAP2H;     // Reload / Capture for Timer 2: upper byte                                  
sfr at 0x98             P5;     // Port 5                                                                    
sfr at 0x99     T0T1CLKCFG;     // Timer 0 and Timer 1 input clock configurations                            
sfr at 0x9A          T0CON;     // Timer 0 configuration register                                            
sfr at 0x9B          T1CON;     // Timer 1 configuration register                                            
sfr at 0x9C          T2CON;     // Timer 2 configuration register                                            
sfr at 0x9D       T2CLKCFG;     // Timer 2 input clock configuration                                         

sfr at 0xA0             P2;     // Port 2                                                                    

sfr at 0xA8         INTEN2;     // Interrupt enable 2                                                        

sfr at 0xB0             P3;     // Port 3                                                                    

sfr at 0xB8      IPINFLAG1;     // Interrupt pin flags 1                                                     
sfr at 0xB9        PORTCHG;     // Interrupt port change                                                     

sfr at 0xC0             P4;     // Port 4                                                                    

sfr at 0xC8             P6;     // Port 6                                                                    

sfr at 0xD0            PSW;     // Program Status Word                                                       

sfr at 0xD6       IPININV1;     // Interrupt pin inversion 1                                                 
sfr at 0xD7       IPININV2;     // Interrupt pin inversion 2                                                 
sfr at 0xD8      IPINFLAG2;     // Interrupt pin flags 2                                                     
sfr at 0xD9       XMEMCTRL;     // Off-chip external memory control                                          

sfr at 0xE0            ACC;     // Accumulator                                                               
sfr at 0xE1       DEVIOMAP;     // Device input/output mapping                                               
sfr at 0xE2        INTPRI1;     // Interrupt priority configuration 1                                        
sfr at 0xE3        INTPRI2;     // Interrupt priority configuration 2                                        
sfr at 0xE4        INTSRC1;     // Interrupt source configuration 1                                          
sfr at 0xE5        INTSRC2;     // Interrupt source configuration 2                                          
sfr at 0xE6      IPINSENS1;     // Interrupt pin sensitivity configuration 1                                   
sfr at 0xE7      IPINSENS2;     // Interrupt pin sensitivity configuration 2                                   
sfr at 0xE8       GENINTEN;     // General interrupt control                                                 
sfr at 0xE9      FPICONFIG;     // Flash programming interface configuration                                 
sfr at 0xEA       FPIADDRL;     // Flash programming address lower byte                                      
sfr at 0xEB       FPIADDRH;     // Flash programming address upper byte                                      
sfr at 0xEC       FPIDATAL;     // Flash programming data lower byte                                         
sfr at 0xED       FPIDATAH;     // Flash programming data upper byte                                         
sfr at 0xEE      FPICLKSPD;     // Flash programming clock speed