📄 mlrs3074.inc
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; File: MLRS3074.inc
; Version: 1.92
; Target: MetaLink 8051 Cross Assembler
; Date: 4/27/2006
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;
; This file provides all of the SFR definitions described in the device
; datsheet.
;
; DO NOT ACCESS REGISTER VALUES NOT ON THIS LIST
; Make sure that the page selected contains the SFR being accessed
;
; Copyright (C) 2006 Ramtron International Corporation
;
; MetaLink 8051 Cross Assembler Copyright (C) 1989 by MetaLink Corp
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; MAKE SURE THIS FILE IS ONLY ACCESSED ONCE PER PROJECT
; SFRs that can be accessed on either page
P0 EQU 080h ; Port 0
SP EQU 081h ; Stack pointer
DPL0 EQU 082h ; Data Pointer 0 lower byte
DPH0 EQU 083h ; Data Pointer 0 upper byte
DPL1 EQU 084h ; Data Pointer 1 lower byte
DPH1 EQU 085h ; Data Pointer 1 upper byte
DPS EQU 086h ; Data Pointer select
PCON EQU 087h ; Power control
INTEN1 EQU 088h ; Interrupt enable 1
T0T1CFG EQU 089h ; Timer 0 and Timer 1 configuration
TL0 EQU 08Ah ; Timer 0 lower byte
TH0 EQU 08Bh ; Timer 0 upper byte
TL1 EQU 08Ch ; Timer 1 lower byte
TH1 EQU 08Dh ; Timer 1 upper byte
TL2 EQU 08Eh ; Timer 2 lower byte
TH2 EQU 08Fh ; Timer 2 upper byte
P1 EQU 090h ; Port 1
WDTCFG EQU 091h ; Watchdog timer configuration
RCAP0L EQU 092h ; Reload / Capture for Timer 0: lower byte
RCAP0H EQU 093h ; Reload / Capture for Timer 0: upper byte
RCAP1L EQU 094h ; Reload / Capture for Timer 1: lower byte
RCAP1H EQU 095h ; Reload / Capture for Timer 1: upper byte
RCAP2L EQU 096h ; Reload / Capture for Timer 2: lower byte
RCAP2H EQU 097h ; Reload / Capture for Timer 2: upper byte
P5 EQU 098h ; Port 5
T0T1CLKCFG EQU 099h ; Timer 0 and Timer 1 input clock configurations
T0CON EQU 09Ah ; Timer 0 configuration register
T1CON EQU 09Bh ; Timer 1 configuration register
T2CON EQU 09Ch ; Timer 2 configuration register
T2CLKCFG EQU 09Dh ; Timer 2 input clock configuration
P2 EQU 0A0h ; Port 2
INTEN2 EQU 0A8h ; Interrupt enable 2
P3 EQU 0B0h ; Port 3
IPINFLAG1 EQU 0B8h ; Interrupt pin flags 1
PORTCHG EQU 0B9h ; Interrupt port change
P4 EQU 0C0h ; Port 4
P6 EQU 0C8h ; Port 6
PSW EQU 0D0h ; Program Status Word
IPININV1 EQU 0D6h ; Interrupt pin inversion 1
IPININV2 EQU 0D7h ; Interrupt pin inversion 2
IPINFLAG2 EQU 0D8h ; Interrupt pin flags 2
XMEMCTRL EQU 0D9h ; Off-chip external memory control
ACC EQU 0E0h ; Accumulator
DEVIOMAP EQU 0E1h ; Device input/output mapping
INTPRI1 EQU 0E2h ; Interrupt priority configuration 1
INTPRI2 EQU 0E3h ; Interrupt priority configuration 2
INTSRC1 EQU 0E4h ; Interrupt source configuration 1
INTSRC2 EQU 0E5h ; Interrupt source configuration 2
IPINSENS1 EQU 0E6h ; Interrupt pin sensitivity configuration 1
IPINSENS2 EQU 0E7h ; Interrupt pin sensitivity configuration 2
GENINTEN EQU 0E8h ; General interrupt control
FPICONFIG EQU 0E9h ; Flash programming interface configuration
FPIADDRL EQU 0EAh ; Flash programming address lower byte
FPIADDRH EQU 0EBh ; Flash programming address upper byte
FPIDATAL EQU 0ECh ; Flash programming data lower byte
FPIDATAH EQU 0EDh ; Flash programming data upper byte
FPICLKSPD EQU 0EEh ; Flash programming clock speed
B EQU 0F0h ; B
MPAGE EQU 0F1h ; External memory page select
DEVCLKCFG1 EQU 0F2h ; Clock configuration 1
DEVCLKCFG2 EQU 0F3h ; Clock configuration 2
PERIPHEN1 EQU 0F4h ; Perhipheral enable 1
PERIPHEN2 EQU 0F5h ; Perhipheral enable 2
DEVMEMCFG EQU 0F6h ; Memory control
PORTINEN EQU 0F7h ; Port input logic enable
USERFLAGS EQU 0F8h ; Additional software flags
P0PINCFG EQU 0F9h ; Port 0 pin configuration
P1PINCFG EQU 0FAh ; Port 1 pin configuration
P2PINCFG EQU 0FBh ; Port 2 pin configuration
P3PINCFG EQU 0FCh ; Port 3 pin configuration
P4PINCFG EQU 0FDh ; Port 4 pin configuration
P5PINCFG EQU 0FEh ; Port 5 pin configuration
P6PINCFG EQU 0FFh ; Port 6 pin configuration
; SFRs that can be only be accessed on PAGE 0
; When DEVMEMCFG bit 0 = 0
PWC0CFG EQU 09Eh; Pulse Width Counter 0 configuration
PWC1CFG EQU 09Fh; Pulse Width Counter 1 configuration
UART0INT EQU 0A1h; UART 0 Interrupt
UART0CFG EQU 0A2h; UART 0 Configure
UART0BUF EQU 0A3h; UART 0 buffer
UART0BRL EQU 0A4h; UART 0 baud rate lower byte
UART0BRH EQU 0A5h; UART 0 baud rate upper byte
UART0EXT EQU 0A6h; UART 0 extentions
PWMCFG EQU 0A9h; Pulse Width Modulator configurations
PWMEN EQU 0AAh; Pulse Width Modulator enable
PWMLDPOL EQU 0ABh; / Pulse Width Modulator polarity
PWMDATA EQU 0ACh; Pulse Width Modulator data
PWMTMREN EQU 0ADh; Pulse Width Modulator timer enable
PWMTMRF EQU 0AEh; Pulse Width Modulator timer overflow flags
PWMCLKCFG EQU 0AFh; Pulse Width Modulator clock config
UART1INT EQU 0B0h; UART 1 Interrupt
UART1CFG EQU 0B1h; UART 1 Configure
UART1BUF EQU 0B2h; UART 1 buffer
UART1BRL EQU 0B3h; UART 1 baud rate lower byte
UART1BRH EQU 0B4h; UART 1 baud rate upper byte
UART1EXT EQU 0B5h; UART 1 extentions
SPICTRL EQU 0C1h; SPI (Serial Perhipheral Interface) control
SPICONFIG EQU 0C2h; SPI configurations
SPISIZE EQU 0C3h; SPI transaction size
SPIRXTX0 EQU 0C4h; SPI recieve / transmit register 0 [Data 7: 0]
SPIRXTX1 EQU 0C5h; SPI recieve / transmit register 0 [Data 15: 8]
SPIRXTX2 EQU 0C6h; SPI recieve / transmit register 0 [Data 23:16]
SPIRXTX3 EQU 0C7h; SPI recieve / transmit register 0 [Data 32:24]
SPISTATUS EQU 0C9h; SPI status
I2CCONFIG EQU 0D1h; I2C (Inter Chip Communication) configuration
I2CTIMING EQU 0D2h; I2C timing
I2CIDCFG EQU 0D3h; I2C indentification
I2CSTATUS EQU 0D4h; I2C status
I2CRXTX EQU 0D5h; I2C recieve / transmit buffer
FRAMCFG1 EQU 0DCh; FRAM configuration 1
FRAMCFG2 EQU 0DDh; FRAM configuration 2
; SFRs that can be only be accessed on PAGE 1
; When DEVMEMCFG bit 0 = 1
AUA0 EQU 0A2h; Arithmetic Unit A [ 7: 0]
AUA1 EQU 0A3h; Arithmetic Unit A [15: 8]
AUC0 EQU 0A4h; Arithmetic Unit C [ 7: 0]
AUC1 EQU 0A5h; Arithmetic Unit C [15: 8]
AUC2 EQU 0A6h; Arithmetic Unit C [23:16]
AUC3 EQU 0A7h; Arithmetic Unit C [32:24]
AUB0DIV EQU 0B1h; Arithmetic Unit B Divide [ 7: 0]
AUB0 EQU 0B2h; Arithmetic Unit B Multiply [ 7: 0]
AUB1 EQU 0B3h; Arithmetic Unit B [15: 8]
AURES0 EQU 0B4h; Arithmetic Unit Result 0
AURES1 EQU 0B5h; Arithmetic Unit Result 1
AURES2 EQU 0B6h; Arithmetic Unit Result 2
AURES3 EQU 0B7h; Arithmetic Unit Result 3
AUSHIFTCFG EQU 0C1h; Arithmetic Unit shift configuration
AUCONFIG1 EQU 0C2h; Arithmetic Unit configuration 1
AUCONFIG2 EQU 0C3h; Arithmetic Unit configuration 2
AUPREV0 EQU 0C4h; Arithmetic Unit previous result 0
AUPREV1 EQU 0C5h; Arithmetic Unit previous result 1
AUPREV2 EQU 0C6h; Arithmetic Unit previous result 2
AUPREV3 EQU 0C7h; Arithmetic Unit previous result 3
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (C) 2006 Ramtron International Corporation
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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