v3k_fram_uart_demo1_sdcc.cdb

DEMO程序 单周期8051内核 8K铁电FRAM 56IO 4KRAM 40MIPS

M:V3K_FRAM_UART_Demo1_SDCC
F:G$main$0$0({2}DF,SV:S),C,0,0,0,0,0
F:G$INT0Interrupt$0$0({2}DF,SV:S),C,0,0,1,0,0
F:G$UART0Interrupt$0$0({2}DF,SV:S),C,0,0,1,5,0
F:G$uart0config$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$txmit0$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$bin2bcdser0$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$Uart0HexSer4$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$Uart0HexSer2$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$delay$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$ReadFram$0$0({2}DF,SC:S),Z,0,0,0,0,0
F:G$WriteFram$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$ReadFramUart0$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$WriteReadFramUart0$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$FramProtect$0$0({2}DF,SV:S),Z,0,0,0,0,0
F:G$FramInit$0$0({2}DF,SI:S),Z,0,0,0,0,0
F:G$FramInit$0$0({2}DF,SI:S),Z,0,0,0,0,0
F:G$FramInit$0$0({2}DF,SI:S),Z,0,0,0,0,0
F:G$FramInit$0$0({2}DF,SI:S),Z,0,0,0,0,0
S:G$framptr$0$0({2}DX,SC:U),E,0,0
S:G$msg$0$0({19}DA19,SC:S),E,0,0
S:G$msgint0$0$0({18}DA18,SC:S),E,0,0
S:Lmain$letter$1$1({1}SC:S),R,0,0,[r2]
S:Lmain$cptr$1$1({2}SI:S),R,0,0,[r3,r4]
S:LINT0Interrupt$bof$1$1({2}SI:S),R,0,0,[]
S:LINT0Interrupt$cptr$1$1({1}SC:S),R,0,0,[r2]
S:LUART0Interrupt$genvar$1$1({1}SC:S),R,0,0,[r3]
S:Lbin2bcdser0$number$1$1({2}SI:U),R,0,0,[r2,r3]
S:Lbin2bcdser0$x$1$1({1}SC:U),R,0,0,[r5]
S:Lbin2bcdser0$zerodisplay$1$1({1}SC:U),R,0,0,[r4]
S:LUart0HexSer4$value$1$1({2}SI:S),R,0,0,[r2,r3]
S:LUart0HexSer4$valmsb$1$1({1}SC:S),R,0,0,[r2]
S:LUart0HexSer4$vallsb$1$1({1}SC:S),R,0,0,[r4]
S:LUart0HexSer4$hexchar$1$1({1}SC:S),R,0,0,[r3]
S:LUart0HexSer2$value$1$1({1}SC:S),R,0,0,[r2]
S:LUart0HexSer2$vallsb$1$1({1}SC:S),R,0,0,[r3]
S:LUart0HexSer2$hexchar$1$1({1}SC:S),R,0,0,[r2]
S:LReadFramUart0$offset$1$1({2}SI:S),R,0,0,[r2,r3]
S:LWriteReadFramUart0$value$1$1({1}SC:S),E,0,0
S:LWriteReadFramUart0$offset$1$1({2}SI:S),R,0,0,[r2,r3]
S:Ldelay$x$1$1({1}SC:U),R,0,0,[r4]
S:Ldelay$dlaisloop$1$1({2}SI:U),R,0,0,[r2,r3]
S:G$frambase$0$0({1}SC:U),F,0,0
S:G$P0$0$0({1}SC:U),I,0,0
S:G$SP$0$0({1}SC:U),I,0,0
S:G$DPL0$0$0({1}SC:U),I,0,0
S:G$DPH0$0$0({1}SC:U),I,0,0
S:G$DPL1$0$0({1}SC:U),I,0,0
S:G$DPH1$0$0({1}SC:U),I,0,0
S:G$DPS$0$0({1}SC:U),I,0,0
S:G$PCON$0$0({1}SC:U),I,0,0
S:G$INTEN1$0$0({1}SC:U),I,0,0
S:G$T0T1CFG$0$0({1}SC:U),I,0,0
S:G$TL0$0$0({1}SC:U),I,0,0
S:G$TH0$0$0({1}SC:U),I,0,0
S:G$TL1$0$0({1}SC:U),I,0,0
S:G$TH1$0$0({1}SC:U),I,0,0
S:G$TL2$0$0({1}SC:U),I,0,0
S:G$TH2$0$0({1}SC:U),I,0,0
S:G$P1$0$0({1}SC:U),I,0,0
S:G$WDTCFG$0$0({1}SC:U),I,0,0
S:G$RCAP0L$0$0({1}SC:U),I,0,0
S:G$RCAP0H$0$0({1}SC:U),I,0,0
S:G$RCAP1L$0$0({1}SC:U),I,0,0
S:G$RCAP1H$0$0({1}SC:U),I,0,0
S:G$RCAP2L$0$0({1}SC:U),I,0,0
S:G$RCAP2H$0$0({1}SC:U),I,0,0
S:G$P5$0$0({1}SC:U),I,0,0
S:G$T0T1CLKCFG$0$0({1}SC:U),I,0,0
S:G$T0CON$0$0({1}SC:U),I,0,0
S:G$T1CON$0$0({1}SC:U),I,0,0
S:G$T2CON$0$0({1}SC:U),I,0,0
S:G$T2CLKCFG$0$0({1}SC:U),I,0,0
S:G$P2$0$0({1}SC:U),I,0,0
S:G$INTEN2$0$0({1}SC:U),I,0,0
S:G$P3$0$0({1}SC:U),I,0,0
S:G$IPINFLAG1$0$0({1}SC:U),I,0,0
S:G$PORTCHG$0$0({1}SC:U),I,0,0
S:G$P4$0$0({1}SC:U),I,0,0
S:G$P6$0$0({1}SC:U),I,0,0
S:G$PSW$0$0({1}SC:U),I,0,0
S:G$IPININV1$0$0({1}SC:U),I,0,0
S:G$IPININV2$0$0({1}SC:U),I,0,0
S:G$IPINFLAG2$0$0({1}SC:U),I,0,0
S:G$XMEMCTRL$0$0({1}SC:U),I,0,0
S:G$ACC$0$0({1}SC:U),I,0,0
S:G$DEVIOMAP$0$0({1}SC:U),I,0,0
S:G$INTPRI1$0$0({1}SC:U),I,0,0
S:G$INTPRI2$0$0({1}SC:U),I,0,0
S:G$INTSRC1$0$0({1}SC:U),I,0,0
S:G$INTSRC2$0$0({1}SC:U),I,0,0
S:G$IPINSENS1$0$0({1}SC:U),I,0,0
S:G$IPINSENS2$0$0({1}SC:U),I,0,0
S:G$GENINTEN$0$0({1}SC:U),I,0,0
S:G$FPICONFIG$0$0({1}SC:U),I,0,0
S:G$FPIADDRL$0$0({1}SC:U),I,0,0
S:G$FPIADDRH$0$0({1}SC:U),I,0,0
S:G$FPIDATAL$0$0({1}SC:U),I,0,0
S:G$FPIDATAH$0$0({1}SC:U),I,0,0
S:G$FPICLKSPD$0$0({1}SC:U),I,0,0
S:G$B$0$0({1}SC:U),I,0,0
S:G$MPAGE$0$0({1}SC:U),I,0,0
S:G$DEVCLKCFG1$0$0({1}SC:U),I,0,0
S:G$DEVCLKCFG2$0$0({1}SC:U),I,0,0
S:G$PERIPHEN1$0$0({1}SC:U),I,0,0
S:G$PERIPHEN2$0$0({1}SC:U),I,0,0
S:G$DEVMEMCFG$0$0({1}SC:U),I,0,0
S:G$PORTINEN$0$0({1}SC:U),I,0,0
S:G$USERFLAGS$0$0({1}SC:U),I,0,0
S:G$P0PINCFG$0$0({1}SC:U),I,0,0
S:G$P1PINCFG$0$0({1}SC:U),I,0,0
S:G$P2PINCFG$0$0({1}SC:U),I,0,0
S:G$P3PINCFG$0$0({1}SC:U),I,0,0
S:G$P4PINCFG$0$0({1}SC:U),I,0,0
S:G$P5PINCFG$0$0({1}SC:U),I,0,0
S:G$P6PINCFG$0$0({1}SC:U),I,0,0
S:G$PWC0CFG$0$0({1}SC:U),I,0,0
S:G$PWC1CFG$0$0({1}SC:U),I,0,0
S:G$UART0INT$0$0({1}SC:U),I,0,0
S:G$UART0CFG$0$0({1}SC:U),I,0,0
S:G$UART0BUF$0$0({1}SC:U),I,0,0
S:G$UART0BRL$0$0({1}SC:U),I,0,0
S:G$UART0BRH$0$0({1}SC:U),I,0,0
S:G$UART0EXT$0$0({1}SC:U),I,0,0
S:G$PWMCFG$0$0({1}SC:U),I,0,0
S:G$PWMEN$0$0({1}SC:U),I,0,0
S:G$PWMLDPOL$0$0({1}SC:U),I,0,0
S:G$PWMDATA$0$0({1}SC:U),I,0,0
S:G$PWMTMREN$0$0({1}SC:U),I,0,0
S:G$PWMTMRF$0$0({1}SC:U),I,0,0
S:G$PWMCLKCFG$0$0({1}SC:U),I,0,0
S:G$UART1INT$0$0({1}SC:U),I,0,0
S:G$UART1CFG$0$0({1}SC:U),I,0,0
S:G$UART1BUF$0$0({1}SC:U),I,0,0
S:G$UART1BRL$0$0({1}SC:U),I,0,0
S:G$UART1BRH$0$0({1}SC:U),I,0,0
S:G$UART1EXT$0$0({1}SC:U),I,0,0
S:G$SPICTRL$0$0({1}SC:U),I,0,0
S:G$SPICONFIG$0$0({1}SC:U),I,0,0
S:G$SPISIZE$0$0({1}SC:U),I,0,0
S:G$SPIRXTX0$0$0({1}SC:U),I,0,0
S:G$SPIRXTX1$0$0({1}SC:U),I,0,0
S:G$SPIRXTX2$0$0({1}SC:U),I,0,0
S:G$SPIRXTX3$0$0({1}SC:U),I,0,0
S:G$SPISTATUS$0$0({1}SC:U),I,0,0
S:G$I2CCONFIG$0$0({1}SC:U),I,0,0
S:G$I2CTIMING$0$0({1}SC:U),I,0,0
S:G$I2CIDCFG$0$0({1}SC:U),I,0,0
S:G$I2CSTATUS$0$0({1}SC:U),I,0,0
S:G$I2CRXTX$0$0({1}SC:U),I,0,0
S:G$FRAMCFG1$0$0({1}SC:U),I,0,0
S:G$FRAMCFG2$0$0({1}SC:U),I,0,0
S:G$AUA0$0$0({1}SC:U),I,0,0
S:G$AUA1$0$0({1}SC:U),I,0,0
S:G$AUC0$0$0({1}SC:U),I,0,0
S:G$AUC1$0$0({1}SC:U),I,0,0
S:G$AUC2$0$0({1}SC:U),I,0,0
S:G$AUC3$0$0({1}SC:U),I,0,0
S:G$AUB0DIV$0$0({1}SC:U),I,0,0
S:G$AUB0$0$0({1}SC:U),I,0,0
S:G$AUB1$0$0({1}SC:U),I,0,0
S:G$AURES0$0$0({1}SC:U),I,0,0
S:G$AURES1$0$0({1}SC:U),I,0,0
S:G$AURES2$0$0({1}SC:U),I,0,0
S:G$AURES3$0$0({1}SC:U),I,0,0
S:G$AUSHIFTCFG$0$0({1}SC:U),I,0,0
S:G$AUCONFIG1$0$0({1}SC:U),I,0,0
S:G$AUCONFIG2$0$0({1}SC:U),I,0,0
S:G$AUPREV0$0$0({1}SC:U),I,0,0
S:G$AUPREV1$0$0({1}SC:U),I,0,0
S:G$AUPREV2$0$0({1}SC:U),I,0,0
S:G$AUPREV3$0$0({1}SC:U),I,0,0
S:G$main$0$0({2}DF,SV:S),C,0,0
S:G$INT0Interrupt$0$0({2}DF,SV:S),C,0,0
S:G$UART0Interrupt$0$0({2}DF,SV:S),C,0,0
L:G$P0$0$0:80
L:G$SP$0$0:81
L:G$DPL0$0$0:82
L:G$DPH0$0$0:83
L:G$DPL1$0$0:84
L:G$DPH1$0$0:85
L:G$DPS$0$0:86
L:G$PCON$0$0:87
L:G$INTEN1$0$0:88
L:G$T0T1CFG$0$0:89
L:G$TL0$0$0:8A
L:G$TH0$0$0:8B
L:G$TL1$0$0:8C
L:G$TH1$0$0:8D
L:G$TL2$0$0:8E
L:G$TH2$0$0:8F
L:G$P1$0$0:90
L:G$WDTCFG$0$0:91
L:G$RCAP0L$0$0:92
L:G$RCAP0H$0$0:93
L:G$RCAP1L$0$0:94
L:G$RCAP1H$0$0:95
L:G$RCAP2L$0$0:96
L:G$RCAP2H$0$0:97
L:G$P5$0$0:98
L:G$T0T1CLKCFG$0$0:99
L:G$T0CON$0$0:9A
L:G$T1CON$0$0:9B
L:G$T2CON$0$0:9C
L:G$T2CLKCFG$0$0:9D
L:G$PWC0CFG$0$0:9E
L:G$PWC1CFG$0$0:9F
L:G$P2$0$0:A0
L:G$UART0INT$0$0:A1
L:G$AUA0$0$0:A2
L:G$UART0CFG$0$0:A2
L:G$AUA1$0$0:A3
L:G$UART0BUF$0$0:A3
L:G$AUC0$0$0:A4
L:G$UART0BRL$0$0:A4
L:G$AUC1$0$0:A5
L:G$UART0BRH$0$0:A5
L:G$AUC2$0$0:A6
L:G$UART0EXT$0$0:A6
L:G$AUC3$0$0:A7
L:G$INTEN2$0$0:A8
L:G$PWMCFG$0$0:A9
L:G$PWMEN$0$0:AA
L:G$PWMLDPOL$0$0:AB
L:G$PWMDATA$0$0:AC
L:G$PWMTMREN$0$0:AD
L:G$PWMTMRF$0$0:AE
L:G$PWMCLKCFG$0$0:AF
L:G$P3$0$0:B0
L:G$UART1INT$0$0:B0
L:G$AUB0DIV$0$0:B1
L:G$UART1CFG$0$0:B1
L:G$AUB0$0$0:B2
L:G$UART1BUF$0$0:B2
L:G$AUB1$0$0:B3
L:G$UART1BRL$0$0:B3
L:G$AURES0$0$0:B4
L:G$UART1BRH$0$0:B4
L:G$AURES1$0$0:B5
L:G$UART1EXT$0$0:B5
L:G$AURES2$0$0:B6
L:G$AURES3$0$0:B7
L:G$IPINFLAG1$0$0:B8
L:G$PORTCHG$0$0:B9
L:G$P4$0$0:C0
L:G$AUSHIFTCFG$0$0:C1
L:G$SPICTRL$0$0:C1
L:G$AUCONFIG1$0$0:C2
L:G$SPICONFIG$0$0:C2
L:G$AUCONFIG2$0$0:C3
L:G$SPISIZE$0$0:C3
L:G$AUPREV0$0$0:C4
L:G$SPIRXTX0$0$0:C4
L:G$AUPREV1$0$0:C5
L:G$SPIRXTX1$0$0:C5
L:G$AUPREV2$0$0:C6
L:G$SPIRXTX2$0$0:C6
L:G$AUPREV3$0$0:C7
L:G$SPIRXTX3$0$0:C7
L:G$P6$0$0:C8
L:G$SPISTATUS$0$0:C9
L:G$PSW$0$0:D0
L:G$I2CCONFIG$0$0:D1
L:G$I2CTIMING$0$0:D2
L:G$I2CIDCFG$0$0:D3
L:G$I2CSTATUS$0$0:D4
L:G$I2CRXTX$0$0:D5
L:G$IPININV1$0$0:D6
L:G$IPININV2$0$0:D7
L:G$IPINFLAG2$0$0:D8
L:G$XMEMCTRL$0$0:D9
L:G$FRAMCFG1$0$0:DC
L:G$FRAMCFG2$0$0:DD
L:G$ACC$0$0:E0
L:G$DEVIOMAP$0$0:E1
L:G$INTPRI1$0$0:E2
L:G$INTPRI2$0$0:E3
L:G$INTSRC1$0$0:E4
L:G$INTSRC2$0$0:E5
L:G$IPINSENS1$0$0:E6
L:G$IPINSENS2$0$0:E7
L:G$GENINTEN$0$0:E8
L:G$FPICONFIG$0$0:E9
L:G$FPIADDRL$0$0:EA
L:G$FPIADDRH$0$0:EB
L:G$FPIDATAL$0$0:EC
L:G$FPIDATAH$0$0:ED
L:G$FPICLKSPD$0$0:EE
L:G$B$0$0:F0
L:G$MPAGE$0$0:F1
L:G$DEVCLKCFG1$0$0:F2
L:G$DEVCLKCFG2$0$0:F3
L:G$PERIPHEN1$0$0:F4
L:G$PERIPHEN2$0$0:F5
L:G$DEVMEMCFG$0$0:F6
L:G$PORTINEN$0$0:F7
L:G$USERFLAGS$0$0:F8
L:G$P0PINCFG$0$0:F9
L:G$P1PINCFG$0$0:FA
L:G$P2PINCFG$0$0:FB
L:G$P3PINCFG$0$0:FC
L:G$P4PINCFG$0$0:FD
L:G$P5PINCFG$0$0:FE
L:G$P6PINCFG$0$0:FF
L:G$frambase$0$0:8000
L:G$framptr$0$0:8
L:G$msg$0$0:A
L:G$msgint0$0$0:1D
L:LWriteReadFramUart0$value$1$1:2F
L:LWriteFram$value$1$1:30
L:A$V3K_FRAM_UART_Demo1_SDCC$502:0
L:A$V3K_FRAM_UART_Demo1_SDCC$503:3
L:A$V3K_FRAM_UART_Demo1_SDCC$505:B
L:A$V3K_FRAM_UART_Demo1_SDCC$507:13
L:A$V3K_FRAM_UART_Demo1_SDCC$509:1B
L:A$V3K_FRAM_UART_Demo1_SDCC$511:23
L:A$V3K_FRAM_UART_Demo1_SDCC$513:2B
L:A$V3K_FRAM_UART_Demo1_SDCC$699:2E
L:A$V3K_FRAM_UART_Demo1_SDCC$701:31
L:A$V3K_FRAM_UART_Demo1_SDCC$726:33
L:C$V3K_FRAM_UART_Demo1_SDCC.c$74$0$0:33
L:C$V3K_FRAM_UART_Demo1_SDCC.c$79$1$1:33
L:G$main$0$0:33
L:A$V3K_FRAM_UART_Demo1_SDCC$730:36
L:C$V3K_FRAM_UART_Demo1_SDCC.c$80$1$1:36
L:A$V3K_FRAM_UART_Demo1_SDCC$734:39
L:C$V3K_FRAM_UART_Demo1_SDCC.c$82$1$1:39
L:A$V3K_FRAM_UART_Demo1_SDCC$738:3C
L:C$V3K_FRAM_UART_Demo1_SDCC.c$87$1$1:3C
L:A$V3K_FRAM_UART_Demo1_SDCC$742:3F
L:C$V3K_FRAM_UART_Demo1_SDCC.c$91$1$1:3F