📄 v3k_fram_demo_4_datash_sdcc.rst
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433 ;--------------------------------------------------------
434 ; indirectly addressable internal ram data
435 ;--------------------------------------------------------
436 .area ISEG (DATA)
437 ;--------------------------------------------------------
438 ; bit data
439 ;--------------------------------------------------------
440 .area BSEG (BIT)
441 ;--------------------------------------------------------
442 ; paged external ram data
443 ;--------------------------------------------------------
444 .area PSEG (PAG,XDATA)
445 ;--------------------------------------------------------
446 ; external ram data
447 ;--------------------------------------------------------
448 .area XSEG (XDATA)
8000 449 G$frambase$0$0 == 0x8000
8000 450 _frambase = 0x8000
451 ;--------------------------------------------------------
452 ; external initialized ram data
453 ;--------------------------------------------------------
454 .area XISEG (XDATA)
455 .area CSEG (CODE)
456 .area GSINIT0 (CODE)
457 .area GSINIT1 (CODE)
458 .area GSINIT2 (CODE)
459 .area GSINIT3 (CODE)
460 .area GSINIT4 (CODE)
461 .area GSINIT5 (CODE)
462 ;--------------------------------------------------------
463 ; interrupt vector
464 ;--------------------------------------------------------
465 .area CSEG (CODE)
0000 466 __interrupt_vect:
0000 02 00 65 467 ljmp __sdcc_gsinit_startup
468 ;--------------------------------------------------------
469 ; global & static initialisations
470 ;--------------------------------------------------------
471 .area CSEG (CODE)
472 .area GSINIT (CODE)
473 .area GSFINAL (CODE)
474 .area GSINIT (CODE)
475 .globl __sdcc_gsinit_startup
476 .globl __sdcc_program_startup
477 .globl __start__stack
478 .globl __mcs51_genXINIT
479 .globl __mcs51_genXRAMCLEAR
480 .globl __mcs51_genRAMCLEAR
0000 481 G$main$0$0 ==.
0000 482 C$V3K_FRAM_Demo_4_Datash_SDCC.c$25$1$1 ==.
483 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:25: xdata unsigned char * data framptr = &frambase ; //Init a pointer in IRAM pointing to the frambase var.
484 ; genAddrOf
00BE 75 08 00 485 mov _framptr,#_frambase
00C1 75 09 80 486 mov (_framptr + 1),#(_frambase >> 8)
487 .area GSFINAL (CODE)
00C4 02 00 03 488 ljmp __sdcc_program_startup
489 ;--------------------------------------------------------
490 ; Home
491 ;--------------------------------------------------------
492 .area HOME (CODE)
493 .area CSEG (CODE)
494 ;--------------------------------------------------------
495 ; code
496 ;--------------------------------------------------------
497 .area CSEG (CODE)
0003 498 __sdcc_program_startup:
0003 12 00 08 499 lcall _main
500 ; return from main will lock up
0006 80 FE 501 sjmp .
502 ;------------------------------------------------------------
503 ;Allocation info for local variables in function 'main'
504 ;------------------------------------------------------------
505 ;cptr Allocated to registers r2 r3
506 ;------------------------------------------------------------
0008 507 G$main$0$0 ==.
0008 508 C$V3K_FRAM_Demo_4_Datash_SDCC.c$32$0$0 ==.
509 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:32: void main (void){
510 ; -----------------------------------------
511 ; function main
512 ; -----------------------------------------
0008 513 _main:
0002 514 ar2 = 0x02
0003 515 ar3 = 0x03
0004 516 ar4 = 0x04
0005 517 ar5 = 0x05
0006 518 ar6 = 0x06
0007 519 ar7 = 0x07
0000 520 ar0 = 0x00
0001 521 ar1 = 0x01
0008 522 C$V3K_FRAM_Demo_4_Datash_SDCC.c$36$1$1 ==.
523 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:36: DEVMEMCFG |= 0xC0; //Activate the FRAM
524 ; genOr
0008 43 F6 C0 525 orl _DEVMEMCFG,#0xC0
000B 526 C$V3K_FRAM_Demo_4_Datash_SDCC.c$40$1$1 ==.
527 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:40: for(cptr = 0; cptr < 0x400; cptr++)
528 ; genAssign
000B 7A 00 529 mov r2,#0x00
000D 7B 00 530 mov r3,#0x00
000F 531 00113$:
532 ; genCmpLt
533 ; genCmp
000F C3 534 clr c
0010 EA 535 mov a,r2
0011 94 00 536 subb a,#0x00
0013 EB 537 mov a,r3
0014 64 80 538 xrl a,#0x80
0016 94 84 539 subb a,#0x84
540 ; genIfxJump
541 ; Peephole 108 removed ljmp by inverse jump logic
0018 50 14 542 jnc 00116$
001A 543 00127$:
001A 544 C$V3K_FRAM_Demo_4_Datash_SDCC.c$41$1$1 ==.
545 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:41: *(framptr+cptr) = 0x55;
546 ; genPlus
547 ; Peephole 236.g used r2 instead of ar2
001A EA 548 mov a,r2
001B 25 08 549 add a,_framptr
001D F5 82 550 mov dpl,a
551 ; Peephole 236.g used r3 instead of ar3
001F EB 552 mov a,r3
0020 35 09 553 addc a,(_framptr + 1)
0022 F5 83 554 mov dph,a
555 ; genPointerSet
556 ; genFarPointerSet
0024 74 55 557 mov a,#0x55
0026 F0 558 movx @dptr,a
0027 559 C$V3K_FRAM_Demo_4_Datash_SDCC.c$40$1$1 ==.
560 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:40: for(cptr = 0; cptr < 0x400; cptr++)
561 ; genPlus
562 ; genPlusIncr
563 ; tail increment optimized
0027 0A 564 inc r2
0028 BA 00 E4 565 cjne r2,#0x00,00113$
002B 0B 566 inc r3
567 ; Peephole 112.b changed ljmp to sjmp
002C 80 E1 568 sjmp 00113$
002E 569 00116$:
002E 570 C$V3K_FRAM_Demo_4_Datash_SDCC.c$45$1$1 ==.
571 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:45: *(framptr + 0x9100) = 0x23;
572 ; genPlus
573 ; genPlus shortcut
002E AA 08 574 mov r2,_framptr
0030 74 91 575 mov a,#0x91
0032 25 09 576 add a,(_framptr + 1)
0034 FB 577 mov r3,a
578 ; genPointerSet
579 ; genFarPointerSet
0035 8A 82 580 mov dpl,r2
0037 8B 83 581 mov dph,r3
0039 74 23 582 mov a,#0x23
003B F0 583 movx @dptr,a
003C 584 C$V3K_FRAM_Demo_4_Datash_SDCC.c$49$1$1 ==.
585 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:49: B = *(framptr + 0x9100);
586 ; genPointerGet
587 ; genFarPointerGet
003C 8A 82 588 mov dpl,r2
003E 8B 83 589 mov dph,r3
0040 E0 590 movx a,@dptr
0041 F5 F0 591 mov _B,a
0043 592 C$V3K_FRAM_Demo_4_Datash_SDCC.c$53$1$1 ==.
593 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:53: FRAMCFG1 = 0x01; //Set FRAMWEL = 1 Enable Write (FRAMOP = 00)
594 ; genAssign
0043 75 DC 01 595 mov _FRAMCFG1,#0x01
0046 596 C$V3K_FRAM_Demo_4_Datash_SDCC.c$54$1$1 ==.
597 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:54: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
0046 598 00101$:
599 ; genAnd
0046 E5 DC 600 mov a,_FRAMCFG1
601 ; genIfxJump
602 ; Peephole 111 removed ljmp by inverse jump logic
0048 30 E7 FB 603 jnb acc.7,00101$
004B 604 00128$:
004B 605 C$V3K_FRAM_Demo_4_Datash_SDCC.c$56$1$1 ==.
606 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:56: FRAMCFG2 = 0x0C; //Configure FRAMCFG2 to protect the entire FRAM
607 ; genAssign
004B 75 DD 0C 608 mov _FRAMCFG2,#0x0C
004E 609 C$V3K_FRAM_Demo_4_Datash_SDCC.c$58$1$1 ==.
610 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:58: FRAMCFG1 = 0x07; //Execute Transfert of FRAMCFG2 module to FRAM Module
611 ; genAssign
004E 75 DC 07 612 mov _FRAMCFG1,#0x07
0051 613 C$V3K_FRAM_Demo_4_Datash_SDCC.c$59$1$1 ==.
614 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:59: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
0051 615 00104$:
616 ; genAnd
0051 E5 DC 617 mov a,_FRAMCFG1
618 ; genIfxJump
619 ; Peephole 111 removed ljmp by inverse jump logic
0053 30 E7 FB 620 jnb acc.7,00104$
0056 621 00129$:
0056 622 C$V3K_FRAM_Demo_4_Datash_SDCC.c$61$1$1 ==.
623 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:61: FRAMCFG1 = 0x03; //Clear FRAMWEL (FRAMOP = 01)
624 ; genAssign
0056 75 DC 03 625 mov _FRAMCFG1,#0x03
0059 626 C$V3K_FRAM_Demo_4_Datash_SDCC.c$62$1$1 ==.
627 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:62: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
0059 628 00107$:
629 ; genAnd
0059 E5 DC 630 mov a,_FRAMCFG1
631 ; genIfxJump
632 ; Peephole 111 removed ljmp by inverse jump logic
005B 30 E7 FB 633 jnb acc.7,00107$
005E 634 00130$:
005E 635 C$V3K_FRAM_Demo_4_Datash_SDCC.c$72$1$1 ==.
636 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:72: while(1);
005E 637 00111$:
638 ; Peephole 112.b changed ljmp to sjmp
005E 80 FE 639 sjmp 00111$
0060 640 00117$:
0060 641 C$V3K_FRAM_Demo_4_Datash_SDCC.c$74$1$1 ==.
0060 642 XG$main$0$0 ==.
0060 22 643 ret
644 .area CSEG (CODE)
645 .area XINIT (CODE)
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