📄 v3k_fram_demo_4_datash_sdcc.asm
字号:
G$UART1INT$0$0 == 0x00b0
_UART1INT = 0x00b0
G$UART1CFG$0$0 == 0x00b1
_UART1CFG = 0x00b1
G$UART1BUF$0$0 == 0x00b2
_UART1BUF = 0x00b2
G$UART1BRL$0$0 == 0x00b3
_UART1BRL = 0x00b3
G$UART1BRH$0$0 == 0x00b4
_UART1BRH = 0x00b4
G$UART1EXT$0$0 == 0x00b5
_UART1EXT = 0x00b5
G$SPICTRL$0$0 == 0x00c1
_SPICTRL = 0x00c1
G$SPICONFIG$0$0 == 0x00c2
_SPICONFIG = 0x00c2
G$SPISIZE$0$0 == 0x00c3
_SPISIZE = 0x00c3
G$SPIRXTX0$0$0 == 0x00c4
_SPIRXTX0 = 0x00c4
G$SPIRXTX1$0$0 == 0x00c5
_SPIRXTX1 = 0x00c5
G$SPIRXTX2$0$0 == 0x00c6
_SPIRXTX2 = 0x00c6
G$SPIRXTX3$0$0 == 0x00c7
_SPIRXTX3 = 0x00c7
G$SPISTATUS$0$0 == 0x00c9
_SPISTATUS = 0x00c9
G$I2CCONFIG$0$0 == 0x00d1
_I2CCONFIG = 0x00d1
G$I2CTIMING$0$0 == 0x00d2
_I2CTIMING = 0x00d2
G$I2CIDCFG$0$0 == 0x00d3
_I2CIDCFG = 0x00d3
G$I2CSTATUS$0$0 == 0x00d4
_I2CSTATUS = 0x00d4
G$I2CRXTX$0$0 == 0x00d5
_I2CRXTX = 0x00d5
G$FRAMCFG1$0$0 == 0x00dc
_FRAMCFG1 = 0x00dc
G$FRAMCFG2$0$0 == 0x00dd
_FRAMCFG2 = 0x00dd
G$AUA0$0$0 == 0x00a2
_AUA0 = 0x00a2
G$AUA1$0$0 == 0x00a3
_AUA1 = 0x00a3
G$AUC0$0$0 == 0x00a4
_AUC0 = 0x00a4
G$AUC1$0$0 == 0x00a5
_AUC1 = 0x00a5
G$AUC2$0$0 == 0x00a6
_AUC2 = 0x00a6
G$AUC3$0$0 == 0x00a7
_AUC3 = 0x00a7
G$AUB0DIV$0$0 == 0x00b1
_AUB0DIV = 0x00b1
G$AUB0$0$0 == 0x00b2
_AUB0 = 0x00b2
G$AUB1$0$0 == 0x00b3
_AUB1 = 0x00b3
G$AURES0$0$0 == 0x00b4
_AURES0 = 0x00b4
G$AURES1$0$0 == 0x00b5
_AURES1 = 0x00b5
G$AURES2$0$0 == 0x00b6
_AURES2 = 0x00b6
G$AURES3$0$0 == 0x00b7
_AURES3 = 0x00b7
G$AUSHIFTCFG$0$0 == 0x00c1
_AUSHIFTCFG = 0x00c1
G$AUCONFIG1$0$0 == 0x00c2
_AUCONFIG1 = 0x00c2
G$AUCONFIG2$0$0 == 0x00c3
_AUCONFIG2 = 0x00c3
G$AUPREV0$0$0 == 0x00c4
_AUPREV0 = 0x00c4
G$AUPREV1$0$0 == 0x00c5
_AUPREV1 = 0x00c5
G$AUPREV2$0$0 == 0x00c6
_AUPREV2 = 0x00c6
G$AUPREV3$0$0 == 0x00c7
_AUPREV3 = 0x00c7
;--------------------------------------------------------
; special function bits
;--------------------------------------------------------
.area RSEG (DATA)
;--------------------------------------------------------
; overlayable register banks
;--------------------------------------------------------
.area REG_BANK_0 (REL,OVR,DATA)
.ds 8
;--------------------------------------------------------
; internal ram data
;--------------------------------------------------------
.area DSEG (DATA)
G$framptr$0$0==.
_framptr::
.ds 2
;--------------------------------------------------------
; overlayable items in internal ram
;--------------------------------------------------------
.area OSEG (OVR,DATA)
;--------------------------------------------------------
; Stack segment in internal ram
;--------------------------------------------------------
.area SSEG (DATA)
__start__stack:
.ds 1
;--------------------------------------------------------
; indirectly addressable internal ram data
;--------------------------------------------------------
.area ISEG (DATA)
;--------------------------------------------------------
; bit data
;--------------------------------------------------------
.area BSEG (BIT)
;--------------------------------------------------------
; paged external ram data
;--------------------------------------------------------
.area PSEG (PAG,XDATA)
;--------------------------------------------------------
; external ram data
;--------------------------------------------------------
.area XSEG (XDATA)
G$frambase$0$0 == 0x8000
_frambase = 0x8000
;--------------------------------------------------------
; external initialized ram data
;--------------------------------------------------------
.area XISEG (XDATA)
.area CSEG (CODE)
.area GSINIT0 (CODE)
.area GSINIT1 (CODE)
.area GSINIT2 (CODE)
.area GSINIT3 (CODE)
.area GSINIT4 (CODE)
.area GSINIT5 (CODE)
;--------------------------------------------------------
; interrupt vector
;--------------------------------------------------------
.area CSEG (CODE)
__interrupt_vect:
ljmp __sdcc_gsinit_startup
;--------------------------------------------------------
; global & static initialisations
;--------------------------------------------------------
.area CSEG (CODE)
.area GSINIT (CODE)
.area GSFINAL (CODE)
.area GSINIT (CODE)
.globl __sdcc_gsinit_startup
.globl __sdcc_program_startup
.globl __start__stack
.globl __mcs51_genXINIT
.globl __mcs51_genXRAMCLEAR
.globl __mcs51_genRAMCLEAR
G$main$0$0 ==.
C$V3K_FRAM_Demo_4_Datash_SDCC.c$25$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:25: xdata unsigned char * data framptr = &frambase ; //Init a pointer in IRAM pointing to the frambase var.
; genAddrOf
mov _framptr,#_frambase
mov (_framptr + 1),#(_frambase >> 8)
.area GSFINAL (CODE)
ljmp __sdcc_program_startup
;--------------------------------------------------------
; Home
;--------------------------------------------------------
.area HOME (CODE)
.area CSEG (CODE)
;--------------------------------------------------------
; code
;--------------------------------------------------------
.area CSEG (CODE)
__sdcc_program_startup:
lcall _main
; return from main will lock up
sjmp .
;------------------------------------------------------------
;Allocation info for local variables in function 'main'
;------------------------------------------------------------
;cptr Allocated to registers r2 r3
;------------------------------------------------------------
G$main$0$0 ==.
C$V3K_FRAM_Demo_4_Datash_SDCC.c$32$0$0 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:32: void main (void){
; -----------------------------------------
; function main
; -----------------------------------------
_main:
ar2 = 0x02
ar3 = 0x03
ar4 = 0x04
ar5 = 0x05
ar6 = 0x06
ar7 = 0x07
ar0 = 0x00
ar1 = 0x01
C$V3K_FRAM_Demo_4_Datash_SDCC.c$36$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:36: DEVMEMCFG |= 0xC0; //Activate the FRAM
; genOr
orl _DEVMEMCFG,#0xC0
C$V3K_FRAM_Demo_4_Datash_SDCC.c$40$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:40: for(cptr = 0; cptr < 0x400; cptr++)
; genAssign
mov r2,#0x00
mov r3,#0x00
00113$:
; genCmpLt
; genCmp
clr c
mov a,r2
subb a,#0x00
mov a,r3
xrl a,#0x80
subb a,#0x84
; genIfxJump
; Peephole 108 removed ljmp by inverse jump logic
jnc 00116$
00127$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$41$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:41: *(framptr+cptr) = 0x55;
; genPlus
; Peephole 236.g used r2 instead of ar2
mov a,r2
add a,_framptr
mov dpl,a
; Peephole 236.g used r3 instead of ar3
mov a,r3
addc a,(_framptr + 1)
mov dph,a
; genPointerSet
; genFarPointerSet
mov a,#0x55
movx @dptr,a
C$V3K_FRAM_Demo_4_Datash_SDCC.c$40$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:40: for(cptr = 0; cptr < 0x400; cptr++)
; genPlus
; genPlusIncr
; tail increment optimized
inc r2
cjne r2,#0x00,00113$
inc r3
; Peephole 112.b changed ljmp to sjmp
sjmp 00113$
00116$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$45$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:45: *(framptr + 0x9100) = 0x23;
; genPlus
; genPlus shortcut
mov r2,_framptr
mov a,#0x91
add a,(_framptr + 1)
mov r3,a
; genPointerSet
; genFarPointerSet
mov dpl,r2
mov dph,r3
mov a,#0x23
movx @dptr,a
C$V3K_FRAM_Demo_4_Datash_SDCC.c$49$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:49: B = *(framptr + 0x9100);
; genPointerGet
; genFarPointerGet
mov dpl,r2
mov dph,r3
movx a,@dptr
mov _B,a
C$V3K_FRAM_Demo_4_Datash_SDCC.c$53$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:53: FRAMCFG1 = 0x01; //Set FRAMWEL = 1 Enable Write (FRAMOP = 00)
; genAssign
mov _FRAMCFG1,#0x01
C$V3K_FRAM_Demo_4_Datash_SDCC.c$54$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:54: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
00101$:
; genAnd
mov a,_FRAMCFG1
; genIfxJump
; Peephole 111 removed ljmp by inverse jump logic
jnb acc.7,00101$
00128$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$56$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:56: FRAMCFG2 = 0x0C; //Configure FRAMCFG2 to protect the entire FRAM
; genAssign
mov _FRAMCFG2,#0x0C
C$V3K_FRAM_Demo_4_Datash_SDCC.c$58$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:58: FRAMCFG1 = 0x07; //Execute Transfert of FRAMCFG2 module to FRAM Module
; genAssign
mov _FRAMCFG1,#0x07
C$V3K_FRAM_Demo_4_Datash_SDCC.c$59$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:59: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
00104$:
; genAnd
mov a,_FRAMCFG1
; genIfxJump
; Peephole 111 removed ljmp by inverse jump logic
jnb acc.7,00104$
00129$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$61$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:61: FRAMCFG1 = 0x03; //Clear FRAMWEL (FRAMOP = 01)
; genAssign
mov _FRAMCFG1,#0x03
C$V3K_FRAM_Demo_4_Datash_SDCC.c$62$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:62: while(!(FRAMCFG1&0x80)); //Wait FREADIDLE == 1 (FRAM IDLE)
00107$:
; genAnd
mov a,_FRAMCFG1
; genIfxJump
; Peephole 111 removed ljmp by inverse jump logic
jnb acc.7,00107$
00130$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$72$1$1 ==.
;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/V3K_FRAM_UART_Demo1_SDCC/V3K_FRAM_Demo_4_Datash_SDCC.c:72: while(1);
00111$:
; Peephole 112.b changed ljmp to sjmp
sjmp 00111$
00117$:
C$V3K_FRAM_Demo_4_Datash_SDCC.c$74$1$1 ==.
XG$main$0$0 ==.
ret
.area CSEG (CODE)
.area XINIT (CODE)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -