📄 v3k_fram_demo_4_datash_sdcc.sym
字号:
ASxxxx Assembler V01.70 + NoICE + SDCC mods + Flat24 Feb-1999 (Intel 8051), page 1.
Symbol Table
A 00D6
B A$V3K_FRAM_Demo_4_Datash_SDCC$467 0000 GR
12 A$V3K_FRAM_Demo_4_Datash_SDCC$485 0000 GR
12 A$V3K_FRAM_Demo_4_Datash_SDCC$486 0003 GR
13 A$V3K_FRAM_Demo_4_Datash_SDCC$488 0000 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$499 0003 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$501 0006 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$525 0008 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$529 000B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$530 000D GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$534 000F GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$535 0010 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$536 0011 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$537 0013 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$538 0014 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$539 0016 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$542 0018 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$548 001A GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$549 001B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$550 001D GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$552 001F GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$553 0020 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$554 0022 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$557 0024 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$558 0026 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$564 0027 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$565 0028 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$566 002B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$568 002C GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$574 002E GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$575 0030 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$576 0032 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$577 0034 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$580 0035 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$581 0037 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$582 0039 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$583 003B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$588 003C GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$589 003E GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$590 0040 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$591 0041 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$595 0043 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$600 0046 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$603 0048 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$608 004B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$612 004E GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$617 0051 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$620 0053 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$625 0056 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$630 0059 GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$633 005B GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$639 005E GR
B A$V3K_FRAM_Demo_4_Datash_SDCC$643 0060 GR
AC 00D6
ACC 00E0
ACC.0 00E0
ACC.1 00E1
ACC.2 00E2
ACC.3 00E3
ACC.4 00E4
ACC.5 00E5
ACC.6 00E6
ACC.7 00E7
B 00F0
B.0 00F0
B.1 00F1
B.2 00F2
B.3 00F3
B.4 00F4
B.5 00F5
B.6 00F6
B.7 00F7
12 C$V3K_FRAM_Demo_4_Datash_SDCC.c$25$1$1 = 0000 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$32$0$0 = 0008 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$36$1$1 = 0008 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$40$1$1 = 0027 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$41$1$1 = 001A GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$45$1$1 = 002E GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$49$1$1 = 003C GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$53$1$1 = 0043 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$54$1$1 = 0046 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$56$1$1 = 004B GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$58$1$1 = 004E GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$59$1$1 = 0051 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$61$1$1 = 0056 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$62$1$1 = 0059 GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$72$1$1 = 005E GR
B C$V3K_FRAM_Demo_4_Datash_SDCC.c$74$1$1 = 0060 GR
CPRL2 00C8
CT2 00C9
CY 00D7
DPH 0083
DPL 0082
EA 00AF
ES 00AC
ET0 00A9
ET1 00AB
ET2 00AD
EX0 00A8
EX1 00AA
EXEN2 00CB
EXF2 00CE
F0 00D5
G$ACC$0$0 = 00E0 G
G$AUA0$0$0 = 00A2 G
G$AUA1$0$0 = 00A3 G
G$AUB0$0$0 = 00B2 G
G$AUB0DIV$0$0 = 00B1 G
G$AUB1$0$0 = 00B3 G
G$AUC0$0$0 = 00A4 G
G$AUC1$0$0 = 00A5 G
G$AUC2$0$0 = 00A6 G
G$AUC3$0$0 = 00A7 G
G$AUCONFIG1$0$0 = 00C2 G
G$AUCONFIG2$0$0 = 00C3 G
G$AUPREV0$0$0 = 00C4 G
G$AUPREV1$0$0 = 00C5 G
G$AUPREV2$0$0 = 00C6 G
G$AUPREV3$0$0 = 00C7 G
G$AURES0$0$0 = 00B4 G
G$AURES1$0$0 = 00B5 G
G$AURES2$0$0 = 00B6 G
G$AURES3$0$0 = 00B7 G
G$AUSHIFTCFG$0$0 = 00C1 G
G$B$0$0 = 00F0 G
G$DEVCLKCFG1$0$0 = 00F2 G
G$DEVCLKCFG2$0$0 = 00F3 G
G$DEVIOMAP$0$0 = 00E1 G
G$DEVMEMCFG$0$0 = 00F6 G
G$DPH0$0$0 = 0083 G
G$DPH1$0$0 = 0085 G
G$DPL0$0$0 = 0082 G
G$DPL1$0$0 = 0084 G
G$DPS$0$0 = 0086 G
G$FPIADDRH$0$0 = 00EB G
G$FPIADDRL$0$0 = 00EA G
G$FPICLKSPD$0$0 = 00EE G
G$FPICONFIG$0$0 = 00E9 G
G$FPIDATAH$0$0 = 00ED G
G$FPIDATAL$0$0 = 00EC G
G$FRAMCFG1$0$0 = 00DC G
G$FRAMCFG2$0$0 = 00DD G
G$GENINTEN$0$0 = 00E8 G
G$I2CCONFIG$0$0 = 00D1 G
G$I2CIDCFG$0$0 = 00D3 G
G$I2CRXTX$0$0 = 00D5 G
G$I2CSTATUS$0$0 = 00D4 G
G$I2CTIMING$0$0 = 00D2 G
G$INTEN1$0$0 = 0088 G
G$INTEN2$0$0 = 00A8 G
G$INTPRI1$0$0 = 00E2 G
G$INTPRI2$0$0 = 00E3 G
G$INTSRC1$0$0 = 00E4 G
G$INTSRC2$0$0 = 00E5 G
G$IPINFLAG1$0$0 = 00B8 G
G$IPINFLAG2$0$0 = 00D8 G
G$IPININV1$0$0 = 00D6 G
G$IPININV2$0$0 = 00D7 G
G$IPINSENS1$0$0 = 00E6 G
G$IPINSENS2$0$0 = 00E7 G
G$MPAGE$0$0 = 00F1 G
G$P0$0$0 = 0080 G
G$P0PINCFG$0$0 = 00F9 G
G$P1$0$0 = 0090 G
G$P1PINCFG$0$0 = 00FA G
G$P2$0$0 = 00A0 G
G$P2PINCFG$0$0 = 00FB G
G$P3$0$0 = 00B0 G
G$P3PINCFG$0$0 = 00FC G
G$P4$0$0 = 00C0 G
G$P4PINCFG$0$0 = 00FD G
G$P5$0$0 = 0098 G
G$P5PINCFG$0$0 = 00FE G
G$P6$0$0 = 00C8 G
G$P6PINCFG$0$0 = 00FF G
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