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📄 v3k_framlcd_demo_sdcc.rst

📁 DEMO程序 单周期8051内核 8K铁电FRAM 56IO 4KRAM 40MIPS
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                    00C7    423 _AUPREV3	=	0x00c7
                            424 ;--------------------------------------------------------
                            425 ; special function bits 
                            426 ;--------------------------------------------------------
                            427 	.area RSEG    (DATA)
                    0082    428 G$LCD_E$0$0 == 0x0082
                    0082    429 _LCD_E	=	0x0082
                    0080    430 G$LCD_RS$0$0 == 0x0080
                    0080    431 _LCD_RS	=	0x0080
                    0081    432 G$LCD_RW$0$0 == 0x0081
                    0081    433 _LCD_RW	=	0x0081
                            434 ;--------------------------------------------------------
                            435 ; overlayable register banks 
                            436 ;--------------------------------------------------------
                            437 	.area REG_BANK_0	(REL,OVR,DATA)
   0000                     438 	.ds 8
                            439 ;--------------------------------------------------------
                            440 ; internal ram data
                            441 ;--------------------------------------------------------
                            442 	.area DSEG    (DATA)
                    0000    443 Lint2lcd$number$1$1==.
   0008                     444 _int2lcd_number_1_1::
   0008                     445 	.ds 2
                    0002    446 G$framptr$0$0==.
   000A                     447 _framptr::
   000A                     448 	.ds 2
                    0004    449 G$lcdval$0$0==.
   000C                     450 _lcdval::
   000C                     451 	.ds 1
                            452 ;--------------------------------------------------------
                            453 ; overlayable items in internal ram 
                            454 ;--------------------------------------------------------
                            455 	.area	OSEG    (OVR,DATA)
                            456 	.area	OSEG    (OVR,DATA)
                            457 ;--------------------------------------------------------
                            458 ; Stack segment in internal ram 
                            459 ;--------------------------------------------------------
                            460 	.area	SSEG	(DATA)
   0010                     461 __start__stack:
   0010                     462 	.ds	1
                            463 
                            464 ;--------------------------------------------------------
                            465 ; indirectly addressable internal ram data
                            466 ;--------------------------------------------------------
                            467 	.area ISEG    (DATA)
                    0000    468 G$cptr$0$0==.
   000F                     469 _cptr::
   000F                     470 	.ds 1
                            471 ;--------------------------------------------------------
                            472 ; bit data
                            473 ;--------------------------------------------------------
                            474 	.area BSEG    (BIT)
                            475 ;--------------------------------------------------------
                            476 ; paged external ram data
                            477 ;--------------------------------------------------------
                            478 	.area PSEG    (PAG,XDATA)
                            479 ;--------------------------------------------------------
                            480 ; external ram data
                            481 ;--------------------------------------------------------
                            482 	.area XSEG    (XDATA)
                    8000    483 G$frambase$0$0 == 0x8000
                    8000    484 _frambase	=	0x8000
                            485 ;--------------------------------------------------------
                            486 ; external initialized ram data
                            487 ;--------------------------------------------------------
                            488 	.area XISEG   (XDATA)
                            489 	.area CSEG    (CODE)
                            490 	.area GSINIT0 (CODE)
                            491 	.area GSINIT1 (CODE)
                            492 	.area GSINIT2 (CODE)
                            493 	.area GSINIT3 (CODE)
                            494 	.area GSINIT4 (CODE)
                            495 	.area GSINIT5 (CODE)
                            496 ;--------------------------------------------------------
                            497 ; interrupt vector 
                            498 ;--------------------------------------------------------
                            499 	.area CSEG    (CODE)
   0000                     500 __interrupt_vect:
   0000 02 05 60            501 	ljmp	__sdcc_gsinit_startup
                            502 ;--------------------------------------------------------
                            503 ; global & static initialisations
                            504 ;--------------------------------------------------------
                            505 	.area CSEG    (CODE)
                            506 	.area GSINIT  (CODE)
                            507 	.area GSFINAL (CODE)
                            508 	.area GSINIT  (CODE)
                            509 	.globl __sdcc_gsinit_startup
                            510 	.globl __sdcc_program_startup
                            511 	.globl __start__stack
                            512 	.globl __mcs51_genXINIT
                            513 	.globl __mcs51_genXRAMCLEAR
                            514 	.globl __mcs51_genRAMCLEAR
                    0000    515 	G$main$0$0 ==.
                    0000    516 	C$V3K_FRAMLCD_DEMO_SDCC.c$67$1$1 ==.
                            517 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/FRAM_LCD_DEMO_SDCC/V3K_FRAMLCD_DEMO_SDCC.c:67: xdata unsigned char * data framptr = &frambase ;		//Init a pointer in IRAM pointing to the frambase var.
                            518 ;     genAddrOf
   05B9 75 0A 00            519 	mov	_framptr,#_frambase
   05BC 75 0B 80            520 	mov	(_framptr + 1),#(_frambase >> 8)
                    0006    521 	G$main$0$0 ==.
                    0006    522 	C$V3K_FRAMLCD_DEMO_SDCC.c$71$1$1 ==.
                            523 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/FRAM_LCD_DEMO_SDCC/V3K_FRAMLCD_DEMO_SDCC.c:71: char lcdval = 0x00;
                            524 ;     genAssign
   05BF 75 0C 00            525 	mov	_lcdval,#0x00
                    0009    526 	G$main$0$0 ==.
                    0009    527 	C$V3K_FRAMLCD_DEMO_SDCC.c$59$1$1 ==.
                            528 ;C:/APP_ENG_Local/Demo_Programs/VRS51L3074/FRAM_LCD_DEMO_SDCC/V3K_FRAMLCD_DEMO_SDCC.c:59: idata   char cptr = 0x00;
                            529 ;     genAssign
   05C2 78 0F               530 	mov	r0,#_cptr
   05C4 76 00               531 	mov	@r0,#0x00
                            532 	.area GSFINAL (CODE)
   05C6 02 00 03            533 	ljmp	__sdcc_program_startup
                            534 ;--------------------------------------------------------
                            535 ; Home
                            536 ;--------------------------------------------------------
                            537 	.area HOME    (CODE)
                            538 	.area CSEG    (CODE)
                            539 ;--------------------------------------------------------
                            540 ; code
                            541 ;--------------------------------------------------------
                            542 	.area CSEG    (CODE)
   0003                     543 __sdcc_program_startup:
   0003 12 04 48            544 	lcall	_main
                            545 ;	return from main will lock up
   0006 80 FE               546 	sjmp .
                            547 ;------------------------------------------------------------
                            548 ;Allocation info for local variables in function 'LCDSlow'
                            549 ;------------------------------------------------------------
                            550 ;cptr                      Allocated to registers r2 
                            551 ;------------------------------------------------------------
                    0008    552 	G$LCDSlow$0$0 ==.
                    0008    553 	C$V2K_CHAR_LCD_P0_SDCC.h$95$0$0 ==.
                            554 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:95: void LCDSlow(void){
                            555 ;	-----------------------------------------
                            556 ;	 function LCDSlow
                            557 ;	-----------------------------------------
   0008                     558 _LCDSlow:
                    0002    559 	ar2 = 0x02
                    0003    560 	ar3 = 0x03
                    0004    561 	ar4 = 0x04
                    0005    562 	ar5 = 0x05
                    0006    563 	ar6 = 0x06
                    0007    564 	ar7 = 0x07
                    0000    565 	ar0 = 0x00
                    0001    566 	ar1 = 0x01
                    0008    567 	C$V2K_CHAR_LCD_P0_SDCC.h$97$1$0 ==.
                            568 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:97: for(cptr = 0x00; cptr < 25; cptr++);
                            569 ;     genAssign
   0008 7A 19               570 	mov	r2,#0x19
   000A                     571 00103$:
                            572 ;     genDjnz
                            573 ;	Peephole 112.b	changed ljmp to sjmp
                            574 ;	Peephole 205	optimized misc jump sequence
   000A DA FE               575 	djnz	r2,00103$
   000C                     576 00108$:
   000C                     577 00109$:
   000C                     578 00104$:
                    000C    579 	C$V2K_CHAR_LCD_P0_SDCC.h$99$1$0 ==.
                    000C    580 	XG$LCDSlow$0$0 ==.
   000C 22                  581 	ret
                            582 ;------------------------------------------------------------
                            583 ;Allocation info for local variables in function 'initlcd'
                            584 ;------------------------------------------------------------
                            585 ;------------------------------------------------------------
                    000D    586 	G$initlcd$0$0 ==.
                    000D    587 	C$V2K_CHAR_LCD_P0_SDCC.h$121$1$0 ==.
                            588 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:121: void initlcd(void)
                            589 ;	-----------------------------------------
                            590 ;	 function initlcd
                            591 ;	-----------------------------------------
   000D                     592 _initlcd:
                    000D    593 	C$V2K_CHAR_LCD_P0_SDCC.h$123$1$1 ==.
                            594 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:123: LCDPORTDIR = 0x00;						//Config LCD port as output
                            595 ;     genAssign
   000D 75 F9 00            596 	mov	_P0PINCFG,#0x00
                    0010    597 	C$V2K_CHAR_LCD_P0_SDCC.h$125$1$1 ==.
                            598 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:125: V2KDelay1ms(20);						// Delay > 15ms
                            599 ;     genCall
                            600 ;	Peephole 182.b	used 16 bit load of dptr
   0010 90 00 14            601 	mov	dptr,#0x0014
   0013 12 04 19            602 	lcall	_V2KDelay1ms
                    0016    603 	C$V2K_CHAR_LCD_P0_SDCC.h$126$1$1 ==.
                            604 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:126: LCDPORT = 0x30;						//;INITIALISATION SEQUENCE BY DEFAULT
                            605 ;     genAssign
   0016 75 80 30            606 	mov	_P0,#0x30
                    0019    607 	C$V2K_CHAR_LCD_P0_SDCC.h$133$1$1 ==.
                            608 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:133: LCDSlow();							//Slow down comm with LCD
                            609 ;     genCall
   0019 12 00 08            610 	lcall	_LCDSlow
                    001C    611 	C$V2K_CHAR_LCD_P0_SDCC.h$134$1$1 ==.
                            612 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:134: LCD_E = 1;							//Send E Pulse
                            613 ;     genAssign
   001C D2 82               614 	setb	_LCD_E
                    001E    615 	C$V2K_CHAR_LCD_P0_SDCC.h$135$1$1 ==.
                            616 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:135: LCDSlow();							//Slow down comm with LCD
                            617 ;     genCall
   001E 12 00 08            618 	lcall	_LCDSlow
                    0021    619 	C$V2K_CHAR_LCD_P0_SDCC.h$136$1$1 ==.
                            620 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:136: LCD_E = 0;
                            621 ;     genAssign
   0021 C2 82               622 	clr	_LCD_E
                    0023    623 	C$V2K_CHAR_LCD_P0_SDCC.h$139$1$1 ==.
                            624 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:139: V2KDelay1ms(5);						// Delay 4.1ms +
                            625 ;     genCall
                            626 ;	Peephole 182.b	used 16 bit load of dptr
   0023 90 00 05            627 	mov	dptr,#0x0005
   0026 12 04 19            628 	lcall	_V2KDelay1ms
                    0029    629 	C$V2K_CHAR_LCD_P0_SDCC.h$140$1$1 ==.
                            630 ;C:/Program Files/SDCC/include/V2K_CHAR_LCD_P0_SDCC.h:140: LCD_E = 1;							//Send E Pulse
                            631 ;     genAssign
   0029 D2 82               632 	setb	_LCD_E
                    002B    633 	C$V2K_CHAR_LCD_P0_SDCC.h$141$1$1 ==.

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