prep2_2.prj

来自「多个Verilog和vhdl程序例子」· PRJ 代码 · 共 23 行

#-- Synplicity, Inc.

#device options
set_option -technology STRATIX
set_option -part EP1S10
set_option -package FC780
set_option -speed_grade -5

#add_file options
add_file -constraint "prep2_2.sdc"
add_file -vhdl -lib work "../common_rtl/prep/prep2_2.vhd"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler true

#map options
set_option -frequency 20.000

#set result format/file last
project -result_format "edif"
project -result_file "prep2_2.edf"