prep2_2.prj

来自「多个Verilog和vhdl程序例子」· PRJ 代码 · 共 24 行

#-- Synplicity, Inc.

#device options
set_option -technology VIRTEX
set_option -part XCV50
set_option -package FG256
set_option -speed_grade -4

#add_file options
add_file -verilog "../common_rtl/prep/prep2_2.v"
add_file -constraint "prep2_2.sdc"

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler true

#map options
set_option -frequency 25.000
set_option -fanout_limit 100
set_option -disable_io_insertion false

#set result format/file last
project -result_file "prep2_2.edf"