prep2_2.prj

多个Verilog和vhdl程序例子

#-- Synplicity, Inc.
#-- Version 7.2 Beta     
#-- Project file E:\work\syn720\examples\verilog\qlogic\prep2_2.prj
#-- Written on Tue Aug 20 16:36:26 2002


#add_file options
add_file -constraint "prep2_2.sdc"
add_file -verilog "../common_rtl/prep/prep2_2.v"


#implementation: "qlogic"
impl -add qlogic

#device options
set_option -technology PASIC1
set_option -part P8X12B
set_option -package pl44
set_option -speed_grade -x

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 20.000
set_option -fanout_limit 16
set_option -disable_io_insertion 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./prep2_2.qdf"

#implementation attributes
set_option -compiler_compatible ""
impl -active "qlogic"