mux.v

来自「多个Verilog和vhdl程序例子」· Verilog 代码 · 共 15 行

module mux(out, a, b, sel);
output out;
input a, b, sel;
reg out;

always @(a or b or sel)
begin
	if (sel)
		out = a;
	else
		out = b;
end

endmodule