tstbench.v

来自「多个Verilog和vhdl程序例子」· Verilog 代码 · 共 14 行

module tstbench;
// instantiate top level design here
`ifdef synthesis
`else
	always #100 clk = ~clk;
	initial
	begin    
		clk = 1;   
		// put rest of stimulus here
	end
`endif
endmodule