latchor2.v

来自「多个Verilog和vhdl程序例子」· Verilog 代码 · 共 13 行

module latchor2(q, a, b, clk);
output q;
input a, b, clk;
reg q;

always @(clk or a or b)
begin
	if (clk)
		q = a | b;
end

endmodule