dff_or.v

来自「多个Verilog和vhdl程序例子」· Verilog 代码 · 共 12 行

module dff_or(q, a, b, clk);
output q;
input a, b, clk;
reg q;

always @(posedge clk)
begin
	q = a | b;
end

endmodule