latch2.v

来自「多个Verilog和vhdl程序例子」· Verilog 代码 · 共 10 行

// Level sensitive latch example 2, with set and reset

module latch2(q, data, clk, set, reset);
output q;
input data, clk, set, reset;

assign q = reset ? 0 : (set ? 1 : (clk ? data : q) );

endmodule