rxunit.map.qmsg

vc++与vhdl代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Sep 21 08:56:52 2007 " "Info: Processing started: Fri Sep 21 08:56:52 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RxUnit -c RxUnit " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RxUnit -c RxUnit" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file clkUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ClkUnit-Behaviour " "Info: Found design unit 1: ClkUnit-Behaviour" {  } { { "clkUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/clkUnit.vhd" 52 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 ClkUnit " "Info: Found entity 1: ClkUnit" {  } { { "clkUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/clkUnit.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "uart_lib.vhd 2 0 " "Info: Found 2 design units, including 0 entities, in source file uart_lib.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 UART_Def " "Info: Found design unit 1: UART_Def" {  } { { "uart_lib.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/uart_lib.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 UART_Def-body " "Info: Found design unit 2: UART_Def-body" {  } { { "uart_lib.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/uart_lib.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RxUnit.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file RxUnit.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 RxUnit-Behaviour " "Info: Found design unit 1: RxUnit-Behaviour" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 58 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 RxUnit " "Info: Found entity 1: RxUnit" {  } { { "RxUnit.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/RxUnit.vhd" 43 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "C:/Documents and Settings/Administrator/桌面/串口vhdl/236149uart from opencores/testhxf/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "RxUnit " "Info: Elaborating entity \"RxUnit\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "80 " "Info: Implemented 80 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "64 " "Info: Implemented 64 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Sep 21 08:56:54 2007 " "Info: Processing ended: Fri Sep 21 08:56:54 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}