at91rm9200_twi.h

at91rm9200 i2c测试程序 ads调试

// ----------------------------------------------------------------------------
// File Name      : AT91RM9200.h
// Object         : AT91RM9200 / TWI definitions
// Writer         : Liuhuiyong
// Date           :2005-1-26
// ----------------------------------------------------------------------------

#ifndef AT91RM9200_TWI_H
#define AT91RM9200_TWI_H

/* Hardware register definition */
typedef volatile unsigned int AT91_REG;

#define AT91C_DS1307_I2C_ADDRESS  	(0x68<<16)
#define AT91C_DS1307_READ_OK			0
#define AT91C_DS1307_WRITE_OK			0
// Global declarations
#define AT91C_MASTER_CLOCK	59904000
#define AT91C_TWI_CLOCK 	100000
#define AT91C_PMC_PLLA      0x000C4F04

int AT91F_TWI_Write (int, char *, int );
int AT91F_TWI_Read  (int, char *, int );

#define AT91C_ID_PIOA   ( 2) // Parallel IO Controller A
#define AT91C_ID_TWI    (12) // Two-Wire Interface
//#define AT91C_BASE_TWI	(0xFFFB8000) // (TWI) Base Address
#define PMC_SCER        (*(unsigned int*)(0xFFFFFC00))  //PMC System Clock Enable Register
#define PMC_SCDR        (*(unsigned int*)(0xFFFFFC04))  //PMC System Clock Disable Register
#define PMC_PCER        (*(unsigned int*)(0xFFFFFC10))  //(PMC) Time Enable Register Address 
#define PMC_PCDR        (*(unsigned int*)(0xFFFFFC14))  //(PMC) Time Disable Register Address 
#define CKGR_MOR        (*(unsigned int*)(0xFFFFFC20))  //Enable The Main Oscillator
#define CKGR_PLLAR      (*(unsigned int*)(0xFFFFFC28))  //Enable The PLLA Clock

#define AIC_IECR        (*(unsigned int*)(0xFFFFF120)) //(AIC) Interrupt Enable Register Address

#define PIO_ASR         (*(unsigned int*)(0xFFFFF470)) //(PIO) Peripheral A Select Register
#define PIO_BSR         (*(unsigned int*)(0xFFFFF474)) //(PIO) Peripheral B Select Register
#define PIO_PDR         (*(unsigned int*)(0xFFFFF404))  //(PIO) Disable Register
#define PIO_MDER        (*(unsigned int*)(0xFFFFF450))  //(PIO) Multi-driver Enable Register
#define PIO_MDDR        (*(unsigned int*)(0xFFFFF454))  //(PIO) Multi-driver Disable Register
#define PIO_PUDR        (*(unsigned int*)(0xFFFFF460))   //PIO Pull Up Disable Register
#define PIO_PUER        (*(unsigned int*)(0xFFFFF464))  //PIO Pull Up Enable Register

#define TWI_CR          (*(unsigned int*)(0xFFFB8000))
#define TWI_MMR         (*(unsigned int*)(0xFFFB8004))
#define TWI_IADR        (*(unsigned int*)(0xFFFB800C))
#define TWI_CWGR        (*(unsigned int*)(0xFFFB8010))
#define TWI_SR          (*(unsigned int*)(0xFFFB8020))
#define TWI_IER         (*(unsigned int*)(0xFFFB8024))
#define TWI_IDR         (*(unsigned int*)(0xFFFB8028))
#define TWI_IMR         (*(unsigned int*)(0xFFFB802C))
#define TWI_RHR         (*(unsigned int*)(0xFFFB8030))
#define TWI_THR         (*(unsigned int*)(0xFFFB8034))

//----------PIO_ASR:(PIO Offset :0x70) PIO Peripheral A Select Register
#define AT91C_PIO_TWD        (0x1 << 25)  //Assigns TWD line to the Peripheral A function.
#define AT91C_PIO_TWCK       (0x1 << 26)  //Assigns TWCK line to the Peripheral A function.
//----------PIO_PDR:(PIO offset :0x04) PIO Disable Register
#define AT91C_PIO_DTWD       (0x1 << 25) // Disable PIO from controlling the TWD pin  
#define AT91C_PIO_DTWCK      (0x1 << 26) // Disable PIO from controlling the TWCK pin 
//---------PIO_MDER:(PIO offset :0x50) PIO Multi-driver Enable Register
#define AT91C_PIO_MTWD       (0x1 << 25) //Enables Multi Drive on the TWD line
#define AT91C_PIO_MTWCK      (0x1 << 26) //Enables Multi Drive on the TWCK line


//----------PMC_SCER:(PMC offset :0x00) PMC System Clock Enable Register
#define AT91C_PMC_PCK         (0x1 << 0)  //Enables the Processor Clock.
//----------PMC_PCER:(PMC offset :0x10) PMC peripheral Clock Enable Register
#define AT91C_PMC_TWI         (0x1<<12)  //Enable TWI Clock 
//----------CKGR_MOR:(PMC offset :0x20) PMC Clock Generator Main Oscillator Register
#define AT91C_PMC_MOSCEN      (0x1 << 0) //Enable The Main Oscillator

//----------AIC_IECR:(ATC offset :0x120) AIC Interrupt Enable Register
#define AT91C_AIC_TWI         (0x1<<12)  //Enable TWI Interrupt


// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
#define AT91C_TWI_START       ( 0x1 <<  0) // (TWI) Send a START Condition
#define AT91C_TWI_STOP        ( 0x1 <<  1) // (TWI) Send a STOP Condition
#define AT91C_TWI_MSEN        ( 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
#define AT91C_TWI_MSDIS       ( 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
#define AT91C_TWI_SWRST       ( 0x1 <<  7) // (TWI) Software Reset
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
#define AT91C_TWI_IADRSZ      ( 0x3 <<  8) // (TWI) Internal Device Address Size
#define 	AT91C_TWI_IADRSZ_NO                   ( 0x0 <<  8) // (TWI) No internal device address
#define 	AT91C_TWI_IADRSZ_1_BYTE               ( 0x1 <<  8) // (TWI) One-byte internal device address
#define 	AT91C_TWI_IADRSZ_2_BYTE               ( 0x2 <<  8) // (TWI) Two-byte internal device address
#define 	AT91C_TWI_IADRSZ_3_BYTE               ( 0x3 <<  8) // (TWI) Three-byte internal device address
#define AT91C_TWI_MREAD       ( 0x1 << 12) // (TWI) Master Read Direction
#define AT91C_TWI_DADR        ( 0x7F <<  16) // (TWI) Device Address
// -------- TWI_IADR : (TWI Offset: 0x8) TWI Internal Address Register --------
#define AT91C_TWI_IADR        ( 0x7F << 16) // (TWI) Internal Address
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
#define AT91C_TWI_CLDIV       ( 0xFF <<  0) // (TWI) Clock Low Divider
#define AT91C_TWI_CHDIV       ( 0xFF <<  8) // (TWI) Clock High Divider
#define AT91C_TWI_CKDIV       ( 0x7 << 16) // (TWI) Clock Divider
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
#define AT91C_TWI_TXCOMP      ( 0x1 <<  0) // (TWI) Transmission Completed
#define AT91C_TWI_RXRDY       ( 0x1 <<  1) // (TWI) Receive holding register ReaDY
#define AT91C_TWI_TXRDY       ( 0x1 <<  2) // (TWI) Transmit holding register ReaDY
#define AT91C_TWI_SVREAD      ( 0x1 <<  3) // (TWI) Slave Read
#define AT91C_TWI_SVACC       ( 0x1 <<  4) // (TWI) Slave Access
#define AT91C_TWI_GCACC       ( 0x1 <<  5) // (TWI) General Call Access
#define AT91C_TWI_OVRE        ( 0x1 <<  6) // (TWI) Overrun Error
#define AT91C_TWI_UNRE        ( 0x1 <<  7) // (TWI) Underrun Error
#define AT91C_TWI_NACK        ( 0x1 <<  8) // (TWI) Not Acknowledged
#define AT91C_TWI_ARBLST      ( 0x1 <<  9) // (TWI) Arbitration Lost
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------

#endif