ad.vhd

FPGA控制串行AD（AD0804）

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ad is
port
(clk:in std_logic;
 reset:in std_logic;
 ad_int:in std_logic;
 data_i:in std_logic_vector(7 downto 0);
 cs,wr,rd:out std_logic;
 en:out std_logic_vector(0 to 3);
 displayA:out std_logic_vector(0 to 6)
);
end;

architecture behave of ad is

signal clk1k1,clk2:std_logic;
signal data_out:std_logic_vector(7 downto 0);
signal numA1,numB1:std_logic_vector(3 downto 0);

component clk1k
port 
(clkin:in std_logic;
 newclk1:out std_logic;
 newclk2:out std_logic
);
end component;

component ad0804
 port(
  reset  : in std_logic;
  clk  : in std_logic;
  ad_int  : in std_logic;
  data_i : in std_logic_vector(7 downto 0);
  data_o : out std_logic_vector(7 downto 0);
  cs  : out std_logic;
  wr  : out std_logic;
  rd  : out std_logic
  );
end component;

component fenwei
port
(numin:in std_logic_vector(7 downto 0);
 numA,numB:out std_logic_vector(3 downto 0)
);
end component;


component display
port
(clock:in std_logic;
 numA,numB,numC,numD:in std_logic_vector(3 downto 0);
 en:out std_logic_vector(0 to 3);--分别接4个数码管的公共端
 display:out std_logic_vector(0 to 6)---接数码管的7个控制端
);
end component;


begin
u1:clk1k port map(clkin=>clk,newclk1=>clk1k1,newclk2=>clk2);
u2:ad0804 port map(reset=>reset,clk=>clk2,ad_int=>ad_int,data_i=>data_i,data_o=>data_out,cs=>cs,wr=>wr,rd=>rd);
u3:fenwei port map(numin=>data_out,numA=>numA1,numB=>numB1);
u4:display port map(clock=>clk1k1,numA=>numA1,numB=>numB1,numC=>"0000",numD=>"0000",en=>en,display=>displayA);

end;