ad.tan.qmsg

FPGA控制串行AD（AD0804）

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk1k:u1\|clk1 " "Info: Detected ripple clock \"clk1k:u1\|clk1\" as buffer" {  } { { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1k:u1\|clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "clk1k:u1\|clk2 " "Info: Detected ripple clock \"clk1k:u1\|clk2\" as buffer" {  } { { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 34 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk1k:u1\|clk2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register clk1k:u1\|counter1\[5\] register clk1k:u1\|counter1\[13\] 95.24 MHz 10.5 ns Internal " "Info: Clock \"clk\" has Internal fmax of 95.24 MHz between source register \"clk1k:u1\|counter1\[5\]\" and destination register \"clk1k:u1\|counter1\[13\]\" (period= 10.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.700 ns + Longest register register " "Info: + Longest register to register delay is 8.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clk1k:u1\|counter1\[5\] 1 REG LC1_J6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_J6; Fanout = 3; REG Node = 'clk1k:u1\|counter1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk1k:u1|counter1[5] } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.500 ns) 2.600 ns clk1k:u1\|Equal0~128 2 COMB LC6_J4 1 " "Info: 2: + IC(1.100 ns) + CELL(1.500 ns) = 2.600 ns; Loc. = LC6_J4; Fanout = 1; COMB Node = 'clk1k:u1\|Equal0~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.600 ns" { clk1k:u1|counter1[5] clk1k:u1|Equal0~128 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 4.500 ns clk1k:u1\|Equal0~123 3 COMB LC7_J4 1 " "Info: 3: + IC(0.000 ns) + CELL(1.900 ns) = 4.500 ns; Loc. = LC7_J4; Fanout = 1; COMB Node = 'clk1k:u1\|Equal0~123'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk1k:u1|Equal0~128 clk1k:u1|Equal0~123 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 6.400 ns clk1k:u1\|Equal0~117 4 COMB LC5_J4 7 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 6.400 ns; Loc. = LC5_J4; Fanout = 7; COMB Node = 'clk1k:u1\|Equal0~117'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk1k:u1|Equal0~123 clk1k:u1|Equal0~117 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.200 ns) 8.700 ns clk1k:u1\|counter1\[13\] 5 REG LC8_J5 2 " "Info: 5: + IC(1.100 ns) + CELL(1.200 ns) = 8.700 ns; Loc. = LC8_J5; Fanout = 2; REG Node = 'clk1k:u1\|counter1\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.300 ns" { clk1k:u1|Equal0~117 clk1k:u1|counter1[13] } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 72.41 % ) " "Info: Total cell delay = 6.300 ns ( 72.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.400 ns ( 27.59 % ) " "Info: Total interconnect delay = 2.400 ns ( 27.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { clk1k:u1|counter1[5] clk1k:u1|Equal0~128 clk1k:u1|Equal0~123 clk1k:u1|Equal0~117 clk1k:u1|counter1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { clk1k:u1|counter1[5] clk1k:u1|Equal0~128 clk1k:u1|Equal0~123 clk1k:u1|Equal0~117 clk1k:u1|counter1[13] } { 0.000ns 1.100ns 0.000ns 0.200ns 1.100ns } { 0.000ns 1.500ns 1.900ns 1.700ns 1.200ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns clk1k:u1\|counter1\[13\] 2 REG LC8_J5 2 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_J5; Fanout = 2; REG Node = 'clk1k:u1\|counter1\[13\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk clk1k:u1|counter1[13] } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[13] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns clk1k:u1\|counter1\[5\] 2 REG LC1_J6 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_J6; Fanout = 3; REG Node = 'clk1k:u1\|counter1\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { clk clk1k:u1|counter1[5] } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[5] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[13] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[5] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.700 ns" { clk1k:u1|counter1[5] clk1k:u1|Equal0~128 clk1k:u1|Equal0~123 clk1k:u1|Equal0~117 clk1k:u1|counter1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.700 ns" { clk1k:u1|counter1[5] clk1k:u1|Equal0~128 clk1k:u1|Equal0~123 clk1k:u1|Equal0~117 clk1k:u1|counter1[13] } { 0.000ns 1.100ns 0.000ns 0.200ns 1.100ns } { 0.000ns 1.500ns 1.900ns 1.700ns 1.200ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[13] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[13] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { clk clk1k:u1|counter1[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.900 ns" { clk clk~out clk1k:u1|counter1[5] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 14 " "Warning: Circuit may not operate. Detected 14 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ad0804:u2\|data_r\[4\] display:u4\|display\[6\] clk 400 ps " "Info: Found hold time violation between source  pin or register \"ad0804:u2\|data_r\[4\]\" and destination pin or register \"display:u4\|display\[6\]\" for clock \"clk\" (Hold time is 400 ps)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.600 ns + Largest " "Info: + Largest clock skew is 4.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.800 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk1k:u1\|clk1 2 REG LC1_J4 14 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC1_J4; Fanout = 14; REG Node = 'clk1k:u1\|clk1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1k:u1|clk1 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.800 ns) + CELL(0.000 ns) 7.800 ns display:u4\|display\[6\] 3 REG LC1_F44 1 " "Info: 3: + IC(4.800 ns) + CELL(0.000 ns) = 7.800 ns; Loc. = LC1_F44; Fanout = 1; REG Node = 'display:u4\|display\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.800 ns" { clk1k:u1|clk1 display:u4|display[6] } "NODE_NAME" } } { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 20.51 % ) " "Info: Total cell delay = 1.600 ns ( 20.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.200 ns ( 79.49 % ) " "Info: Total interconnect delay = 6.200 ns ( 79.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk clk1k:u1|clk1 display:u4|display[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { clk clk~out clk1k:u1|clk1 display:u4|display[6] } { 0.000ns 0.000ns 1.400ns 4.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.200 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 21; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "ad.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.100 ns) 3.000 ns clk1k:u1\|clk2 2 REG LC3_F41 13 " "Info: 2: + IC(1.400 ns) + CELL(1.100 ns) = 3.000 ns; Loc. = LC3_F41; Fanout = 13; REG Node = 'clk1k:u1\|clk2'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { clk clk1k:u1|clk2 } "NODE_NAME" } } { "clk1k.vhd" "" { Text "F:/QuartusII work/AD0804/AD/clk1k.vhd" 34 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.000 ns) 3.200 ns ad0804:u2\|data_r\[4\] 3 REG LC6_F41 1 " "Info: 3: + IC(0.200 ns) + CELL(0.000 ns) = 3.200 ns; Loc. = LC6_F41; Fanout = 1; REG Node = 'ad0804:u2\|data_r\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { clk1k:u1|clk2 ad0804:u2|data_r[4] } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 50.00 % ) " "Info: Total cell delay = 1.600 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 50.00 % ) " "Info: Total interconnect delay = 1.600 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { clk clk1k:u1|clk2 ad0804:u2|data_r[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.200 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|data_r[4] } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk clk1k:u1|clk1 display:u4|display[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { clk clk~out clk1k:u1|clk1 display:u4|display[6] } { 0.000ns 0.000ns 1.400ns 4.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { clk clk1k:u1|clk2 ad0804:u2|data_r[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.200 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|data_r[4] } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns - Shortest register register " "Info: - Shortest register to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ad0804:u2\|data_r\[4\] 1 REG LC6_F41 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_F41; Fanout = 1; REG Node = 'ad0804:u2\|data_r\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ad0804:u2|data_r[4] } "NODE_NAME" } } { "ad0804.vhd" "" { Text "F:/QuartusII work/AD0804/AD/ad0804.vhd" 98 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 1.900 ns display:u4\|Mux7~53 2 COMB LC1_F41 7 " "Info: 2: + IC(0.200 ns) + CELL(1.700 ns) = 1.900 ns; Loc. = LC1_F41; Fanout = 7; COMB Node = 'display:u4\|Mux7~53'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.900 ns" { ad0804:u2|data_r[4] display:u4|Mux7~53 } "NODE_NAME" } } { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.000 ns) 4.000 ns display:u4\|display\[6\] 3 REG LC1_F44 1 " "Info: 3: + IC(1.100 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC1_F44; Fanout = 1; REG Node = 'display:u4\|display\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.100 ns" { display:u4|Mux7~53 display:u4|display[6] } "NODE_NAME" } } { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.700 ns ( 67.50 % ) " "Info: Total cell delay = 2.700 ns ( 67.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns ( 32.50 % ) " "Info: Total interconnect delay = 1.300 ns ( 32.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { ad0804:u2|data_r[4] display:u4|Mux7~53 display:u4|display[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.000 ns" { ad0804:u2|data_r[4] display:u4|Mux7~53 display:u4|display[6] } { 0.000ns 0.200ns 1.100ns } { 0.000ns 1.700ns 1.000ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "display.vhd" "" { Text "F:/QuartusII work/AD0804/AD/display.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.800 ns" { clk clk1k:u1|clk1 display:u4|display[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.800 ns" { clk clk~out clk1k:u1|clk1 display:u4|display[6] } { 0.000ns 0.000ns 1.400ns 4.800ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.200 ns" { clk clk1k:u1|clk2 ad0804:u2|data_r[4] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.200 ns" { clk clk~out clk1k:u1|clk2 ad0804:u2|data_r[4] } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.100ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.000 ns" { ad0804:u2|data_r[4] display:u4|Mux7~53 display:u4|display[6] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.000 ns" { ad0804:u2|data_r[4] display:u4|Mux7~53 display:u4|display[6] } { 0.000ns 0.200ns 1.100ns } { 0.000ns 1.700ns 1.000ns } } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0}