ad0804.vhd

FPGA控制串行AD（AD0804）

--下面给出一个用VHDL实现ADC0804控制器的完整设计过程



--4个状态如下：
--
--idle: CS="0",WR=0,RD=1 启动AD0804开始转换

--convert：CS=1,WR=1,RD=1,AD0804进行数据转换

--read1:  CS="0",WR=1,RD=0,INTR,转换结束，开始读

--read2: CS="1",WR=1,RD=1,读取数据。

--ADC0804的输入时钟没有固定要求，一般为640KHZ、750KHZ



--------------------------------------------------------------------------------
-- Designer Name:    bankqd  
-- Module Name:    ad0804 - Behave
-- Description:    This VHDL design is created to implement a state machine
--                 to control AD0804
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ad0804 is
 port(
  reset  : in std_logic;
  clk  : in std_logic;
  ad_int  : in std_logic;
  data_i : in std_logic_vector(7 downto 0);
  data_o : out std_logic_vector(7 downto 0);
  cs  : out std_logic;
  wr  : out std_logic;
  rd  : out std_logic
  );
end;

architecture Behave of ad0804 is

type state is (start, convert, read1, read2);
signal current_state, next_state : state;
signal data_r : std_logic_vector(7 downto 0);
signal read_data : std_logic;

begin
 sync :process(reset,clk)
 begin
  if(reset = '1') then
   current_state <= start;
  elsif(clk'event and clk = '1') then
   current_state <= next_state;
  end if;
 end process sync;

 comb :process(current_state, ad_int)
 begin
  case current_state is
   when start => 
    next_state <= convert;
    cs <= '0';
    wr <= '0';
    rd <= '1';
    read_data <= '0';
   when convert =>
    if(ad_int = '0') then
     next_state <= read1;
    else
     next_state <= convert;
    end if;
    cs <= '1';
    wr <= '1';
    rd <= '1';
    read_data <= '0';
   when read1 =>
    next_state <= read2;
    cs <= '0';
    wr <= '1';
    rd <= '0';
    read_data <= '1';
   when read2 =>
    next_state <= start;
    cs <= '1';
    wr <= '1';
    rd <= '1';
    read_data <= '0';
   when others =>
    next_state <= start;
  end case;
 end process comb;

 get_data: process(reset,clk)
 begin
  if(reset = '1') then
   data_r <= X"00";
  elsif(clk'event and clk = '1') then
   if(read_data = '1') then
    data_r <= data_i;
   end if;
  end if;
 end process;

 data_o <= data_r;
end;