ad.tan.summary

FPGA控制串行AD（AD0804）

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.100 ns
From           : ad_int
To             : ad0804:u2|current_state.convert
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 20.900 ns
From           : display:u4|display[6]
To             : displayA[6]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.800 ns
From           : data_i[5]
To             : ad0804:u2|data_r[5]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 95.24 MHz ( period = 10.500 ns )
From           : clk1k:u1|counter1[5]
To             : clk1k:u1|counter1[13]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : ad0804:u2|data_r[4]
To             : display:u4|display[6]
From Clock     : clk
To Clock       : clk
Failed Paths   : 14

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 14

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