ying.mpf

fpga功能实现有限字长响应FIR

; will appear as memories.
; The default is 1 (display enumerated type arrays as memories).
; ShowEnumMem = 0

; Specify whether or not arrays of 3 or more dimensions will appear as memories.
; The default is 1 (display 3D+ type arrays as memories).
; Show3DMem = 0

; Turn on/off undebuggable SystemC type warnings. Default is on.
; ShowUndebuggableScTypeWarning = 0

; Turn on/off unassociated SystemC name warnings. Default is off.
; ShowUnassociatedScNameWarning = 1

; Turn on/off PSL assertion pass enable. Default is off.
; AssertionPassEnable = 1

; Turn on/off PSL assertion fail enable. Default is on.
; AssertionFailEnable = 0

; Set PSL assertion pass limit. Default is 1.
; Any positive integer, -1 for infinity.
; AssertionPassLimit = -1

; Set PSL assertion fail limit. Default is 1.
; Any positive integer, -1 for infinity.
; AssertionFailLimit = -1

; Turn on/off PSL assertion pass log. Default is on.
; AssertionPassLog = 0

; Turn on/off PSL assertion fail log. Default is on.
; AssertionFailLog = 0

; Set action type for PSL assertion fail action. Default is continue.
; 0 = Continue  1 = Break  2 = Exit
; AssertionFailAction = 1

; Turn on/off code coverage
; CodeCoverage = 0

; Count all code coverage condition and expression truth table rows that match.
; CoverCountAll = 1

; Turn on/off all PSL cover directive enables.  Default is on.
; CoverEnable = 0

; Turn on/off PSL cover log.  Default is off.
; CoverLog = 1

; Set "at_least" value for all PSL cover directives.  Default is 1.
; CoverAtLeast = 2

; Set weight for all PSL cover directives.  Default is 1.
; CoverWeight = 2

; Check vsim plusargs.  Default is 0 (off).
; 0 = Don't check plusargs
; 1 = Warning on unrecognized plusarg
; 2 = Error and exit on unrecognized plusarg
; CheckPlusargs = 1

; Load the specified shared objects with the RTLD_GLOBAL flag.
; This gives global visibility to all symbols in the shared objects,
; meaning that subsequently loaded shared objects can bind to symbols
; in the global shared objects.  The list of shared objects should
; be whitespace delimited.  This option is not supported on the
; Windows or AIX platforms.
; GlobalSharedObjectList = example1.so example2.so example3.so

[lmc]
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software
libsm = $MODEL_TECH/libsm.sl
; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
; libsm = $MODEL_TECH/libsm.dll
;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
;  Logic Modeling's SmartModel SWIFT software (Windows NT)
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
;  Logic Modeling's SmartModel SWIFT software (Linux)
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

; ModelSim's interface to Logic Modeling's hardware modeler SFI software
libhm = $MODEL_TECH/libhm.sl
; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
; libhm = $MODEL_TECH/libhm.dll
;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
;  Logic Modeling's hardware modeler SFI software (Windows NT)
; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
;  Logic Modeling's hardware modeler SFI software (Linux)
; libsfi = <sfi_dir>/lib/linux/libsfi.so

[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
;   note = 3009
;   warning = 3033
;   error = 3010,3016
;   suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.

[Project]
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 30
Project_File_0 = E:/homework/fpga/top_tp.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336809306 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_showsource 0 vlog_hazard 0 ood 0 vlog_options {} compile_to work vlog_upper 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = E:/homework/fpga/CSA4_tp.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178796346 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = E:/homework/fpga/booth_code.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178869018 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = E:/homework/fpga/half_add1_tp.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178793138 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = E:/homework/fpga/add_20b_tp.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336744370 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = E:/homework/fpga/booth_tp.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336743573 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = E:/homework/fpga/booth_code_tp.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178864696 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = E:/homework/fpga/wallce_tree_tp.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336744031 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = E:/homework/fpga/add_8b.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178868902 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = E:/homework/fpga/top.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336806283 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_showsource 0 vlog_hazard 0 ood 0 vlog_options {} compile_to work vlog_upper 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = E:/homework/fpga/CSA4.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1208071748 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = E:/homework/fpga/mux_x_tp.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336800749 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_showsource 0 vlog_hazard 0 ood 0 vlog_options {} compile_to work vlog_upper 0 compile_order 26 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = E:/homework/fpga/mux_h_tp.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336743026 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = E:/homework/fpga/full_add1.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1208069848 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 19 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = E:/homework/fpga/control_tp.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336805585 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = E:/homework/fpga/add_8b_tp.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178868946 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = E:/homework/fpga/wallce_tree.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336742311 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = E:/homework/fpga/full_add1_tp.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178793112 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = E:/homework/fpga/enter_x_tp.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178799398 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_19 = E:/homework/fpga/Dff.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336805730 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_20 = E:/homework/fpga/add_12b_tp.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178869808 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = E:/homework/fpga/mux_x.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336800754 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_showsource 0 vlog_hazard 0 ood 0 vlog_options {} compile_to work vlog_upper 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_22 = E:/homework/fpga/mux_h.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336742958 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 23 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_23 = E:/homework/fpga/control.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336805480 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = E:/homework/fpga/Dff_tp.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336805814 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_showsource 0 vlog_hazard 0 ood 0 vlog_options {} compile_to work vlog_upper 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_25 = E:/homework/fpga/half_add1.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1208675364 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = E:/homework/fpga/add_20b.v
Project_File_P_26 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336744307 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_27 = E:/homework/fpga/booth.v
Project_File_P_27 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1336743767 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_28 = E:/homework/fpga/enter_x.v
Project_File_P_28 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178798872 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_29 = E:/homework/fpga/add_12b.v
Project_File_P_29 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1178869824 vlog_noload 0 cover_branch 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick = 
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick = 
PSL_DoubleClick = Edit
PSL_CustomDoubleClick = 
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick = 
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick = 
TCL_DoubleClick = Edit
TCL_CustomDoubleClick = 
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick = 
VCD_DoubleClick = Edit
VCD_CustomDoubleClick = 
SDF_DoubleClick = Edit
SDF_CustomDoubleClick = 
XML_DoubleClick = Edit
XML_CustomDoubleClick = 
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick = 
EditorState = {tabbed horizontal 1} {E:/homework/fpga/top_tp.v 0 0} {E:/homework/fpga/enter_x.v 0 0} {E:/homework/fpga/top.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 0