top.v

fpga功能实现有限字长响应FIR

module top(reset_ini,clk1,clk2,in,out,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x_i,x_Ni,x,h,P_i,OE,reset,i,part_sum,sum);
input clk1,clk2,reset_ini;
input[7:0] in;

output[7:0] x_i,x_Ni;
wire[7:0] x_i,x_Ni;
output[8:0] x;
wire[8:0] x;
output[7:0] h;
wire[7:0] h;
output[16:0] P_i;
wire[16:0] P_i;
output[18:0] part_sum;
wire[18:0] part_sum;
output[18:0] sum;
wire[18:0] sum;
output OE;
output reset;
output[2:0] i;
wire[2:0] i;
output[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15;
wire[7:0] x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15;

output[18:0] out;
wire[18:0] out;


enter_x enter_inst(reset_ini,clk1,in,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15);
mux_x mux_x_inst(i,x_i,x_Ni,x0,x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15);
add_8b add_8b_inst(x_i,x_Ni,0,x,co);
mux_h mux_h_inst(i,h);
wallce_tree wallce_inst(x,h,P_i);
add_20b add_20b_inst(P_i,part_sum,sum);
control control_inst(clk1,clk2,i,OE,reset);
Dff dff_inst_1(clk2,reset,sum,part_sum);
Dff dff_inst_2(OE,reset,part_sum,out);
endmodule