dff_tp.v

fpga功能实现有限字长响应FIR

`timescale 1ns/1ns
module Dff_tp();
reg clk,reset;
reg[18:0] D;
wire[18:0] Q;
Dff inst_cnt(clk,reset,D,Q);
initial
  begin
  reset=0;clk=0;D=19'b1100100101010100010;
  #100 reset=1;
  #100 D=19'b1110000111010111010;
  #10 reset=0;
  #10 reset=1;D=19'b1000000101010111010;
  #10 $stop;
  end
 always #5 clk=~clk;
  endmodule