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📁 fpga功能实现有限字长响应FIR
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123 
# Compile of half_adder.v was successful.
# Compile of half_adder_tp.v was successful.
# Compile of i_jishu.v was successful.
# Compile of jishuqi.v was successful.
# Compile of jishuqi_tp.v was successful.
# Compile of multi.v was successful.
# Compile of multi_tp.v was successful.
# Compile of top.v was successful.
# Compile of top_tp.v was successful.
# Compile of x_select.v was successful.
# Compile of x_select_tp.v was successful.
# 42 compiles, 0 failed with no errors. 
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.add
# ** Warning: (vsim-3009) [TSCALE] - Module 'add' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# Loading work.full_adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'full_adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2/f1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Fatal: (vsim-3365) E:/modelsim/work_5_17zhu/add20.v(14): Too many port connections. Expected 3, found 4.
#    Time: 0 ns  Iteration: 0  Instance: /add20_tp/my_add20/a2 File: E:/modelsim/work_5_17zhu/add.v
# FATAL ERROR while loading design
# Error loading design
# Compile of add.v was successful.
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.add
# ** Warning: (vsim-3009) [TSCALE] - Module 'add' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# Loading work.full_adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'full_adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2/f1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
# Compile of add.v was successful.
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
# 2 compiles, 0 failed with no errors. 
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
# 2 compiles, 0 failed with no errors. 
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
123

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