transcript

fpga功能实现有限字长响应FIR

# Reading D:/Program Files/modelsim/win32/../tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0c Feb  2 2005 
# //
# //  Copyright Mentor Graphics Corporation 2005
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
#  OpenFile "E:/modelsim/fpga/add_20b.v" 
# reading modelsim.ini
# Loading project hh
# Compile of add12.v was successful.
# Compile of add12_tp.v was successful.
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
# Compile of add.v was successful.
# Compile of add_tp.v was successful.
# Compile of adder8_for20.v was successful.
# Compile of adder8_for20_tp.v was successful.
# Compile of adder12.v was successful.
# Compile of adder12_for20.v was successful.
# Compile of adder12_for20_tp.v was successful.
# Compile of adder.v was successful.
# Compile of adder_4.v was successful.
# Compile of adder_4_tp.v was successful.
# Compile of adder_tp.v was successful.
# Compile of boothe.v was successful.
# Compile of boothe_tp.v was successful.
# Compile of bt_change.v was successful.
# Compile of bt_change_tp.v was successful.
# Compile of change_N.v was successful.
# Compile of change_N_tp.v was successful.
# Compile of chufaqi1.v was successful.
# Compile of chufaqi1_tp.v was successful.
# Compile of chufaqi2.v was successful.
# Compile of chufaqi2_tp.v was successful.
# Compile of clk2_mux_h.v was successful.
# Compile of clk2_mux_h_tp.v was successful.
# Compile of control.v was successful.
# Compile of control_tp.v was successful.
# Compile of full_adder.v was successful.
# Compile of full_adder_tp.v was successful.
# Compile of half_adder.v was successful.
# Compile of half_adder_tp.v was successful.
# Compile of i_jishu.v was successful.
# Compile of jishuqi.v was successful.
# Compile of jishuqi_tp.v was successful.
# Compile of multi.v was successful.
# Compile of multi_tp.v was successful.
# Compile of top.v was successful.
# Compile of top_tp.v was successful.
# Compile of x_select.v was successful.
# Compile of x_select_tp.v was successful.
# 42 compiles, 0 failed with no errors. 
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# Loading work.full_adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'full_adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2/f1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
# Compile of add20.v was successful.
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# Loading work.full_adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'full_adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2/f1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
# Compile of adder8_for20.v was successful.
# Compile of adder8_for20_tp.v was successful.
vsim work.adder8_for20_tp
# vsim work.adder8_for20_tp 
# Loading work.adder8_for20_tp
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /adder8_for20_tp/my_adder8_for20
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /adder8_for20_tp/my_adder8_for20/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /adder8_for20_tp/my_adder8_for20/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /adder8_for20_tp/my_adder8_for20/a3
run -all
# Break at E:/modelsim/work_5_17zhu/adder8_for20_tp.v line 18
quit -sim
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
vsim work.add20_tp
# vsim work.add20_tp 
# Loading work.add20_tp
# Loading work.add20
# ** Warning: (vsim-3009) [TSCALE] - Module 'add20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20
# Loading work.adder12_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder12_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1
# Loading work.adder
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1
# Loading work.adder_4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder_4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# Loading work.adder8_for20
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder8_for20' does not have a `timescale directive in effect, but previous modules do.
#         Region: /add20_tp/my_add20/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/add20_tp.v(9): [PCDPC] - Port size (20 or 20) does not match connection size (16) for port 'b'.
#         Region: /add20_tp/my_add20
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(8): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a1
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(9): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_1/a3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder12_for20.v(12): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a1/a_3
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(10): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a2
# ** Warning: (vsim-3015) E:/modelsim/work_5_17zhu/adder8_for20.v(11): [PCDPC] - Port size (1 or 1) does not match connection size (32) for port 'cin'.
#         Region: /add20_tp/my_add20/a2/a3
run -all
# Break at E:/modelsim/work_5_17zhu/add20_tp.v line 16
quit -sim
# Compile of add20.v was successful.
# Compile of add12.v was successful.
# Compile of add12_tp.v was successful.
# Compile of add20.v was successful.
# Compile of add20_tp.v was successful.
# Compile of add.v was successful.
# Compile of add_tp.v was successful.
# Compile of adder8_for20.v was successful.
# Compile of adder8_for20_tp.v was successful.
# Compile of adder12.v was successful.
# Compile of adder12_for20.v was successful.
# Compile of adder12_for20_tp.v was successful.
# Compile of adder.v was successful.
# Compile of adder_4.v was successful.
# Compile of adder_4_tp.v was successful.
# Compile of adder_tp.v was successful.
# Compile of boothe.v was successful.
# Compile of boothe_tp.v was successful.
# Compile of bt_change.v was successful.
# Compile of bt_change_tp.v was successful.
# Compile of change_N.v was successful.
# Compile of change_N_tp.v was successful.
# Compile of chufaqi1.v was successful.
# Compile of chufaqi1_tp.v was successful.
# Compile of chufaqi2.v was successful.
# Compile of chufaqi2_tp.v was successful.
# Compile of clk2_mux_h.v was successful.
# Compile of clk2_mux_h_tp.v was successful.
# Compile of control.v was successful.
# Compile of control_tp.v was successful.
# Compile of full_adder.v was successful.
# Compile of full_adder_tp.v was successful.