dff.v

fpga功能实现有限字长响应FIR

module Dff(clk,reset,D,Q);
input clk,reset;
input[18:0] D;
output[18:0] Q;
reg[18:0] Q;
reg temp;
always @(negedge reset or posedge clk)
  begin 
     if(!reset) begin Q<=0;end
     else Q<=D;
  end
 endmodule