full_add1_tp.v

来自「fpga功能实现有限字长响应FIR」· Verilog 代码 · 共 19 行

`timescale 1ns/1ns
module full_add1_tp();
reg a,b,cin;
wire sum,cout;
full_add1  inst_cnt(a,b,cin,sum,cout);
initial 
 begin
      a=0;b=0;cin=0;
#10   a=0;b=0;cin=1;
#10   a=0;b=1;cin=0;
#10   a=0;b=1;cin=1;
#10   a=1;b=0;cin=0;
#10   a=1;b=0;cin=1;
#10   a=1;b=1;cin=0;
#10   a=1;b=1;cin=1;
#10  $stop;
end
endmodule