wallace_tree_tp.v

来自「fpga功能实现有限字长响应FIR」· Verilog 代码 · 共 14 行

`timescale 1ns/1ns
module wallace_tree_tp();
reg[2:0] i;
reg clk2;
reg[8:0] x;
wire[15:0] out;
wallace_tree tree_1(i,clk2,x,out);
initial 
   begin
     i=0;clk2=0;x=9'b010100101;
     #10 i=1;
     #10 i=2;    
   end
always #5 clk2=~clk2;