add_20b_tp.v

来自「fpga功能实现有限字长响应FIR」· Verilog 代码 · 共 15 行

`timescale 1ns/1ns
module add_20b_tp();
reg[16:0] a;
reg[18:0] b;
wire[18:0] out;
add_20b  inst_cnt(a,b,out);
initial 
 begin
      a=17'b01000101011001000; b=19'b1001000101011001000;
#10   a=17'b01000101001001000; b=19'b0010101001011001000;
#10   a=17'b01010101011001000; b=19'b0110101001000011101;
#10   a=17'b10101000111001000; b=19'b1101000100101010011;
#10  $stop;
end
endmodule