_primary.vhd

来自「fpga功能实现有限字长响应FIR」· VHDL 代码 · 共 16 行

library verilog;
use verilog.vl_types.all;
entity control is
    generic(
        state_reset     : integer := 9;
        state_spare     : integer := 8
    );
    port(
        clk1            : in     vl_logic;
        clk2            : in     vl_logic;
        i               : out    vl_logic_vector(2 downto 0);
        OE              : out    vl_logic;
        reset           : out    vl_logic
    );
end control;